ISP1161A1BM ST-Ericsson Inc, ISP1161A1BM Datasheet - Page 104

• Manufacturer Part Number: ISP1161A1BM
• Description: IC USB HOST/DEVICE CTRLR 64-LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1161A1BM

• Controller Type: USB 2.0 Controller
• Interface: Parallel
• Voltage - Supply: 3.3V, 5V
• Current - Supply: 47mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-1163; ISP1161A1BM,557

Philips Semiconductors
Table 96:
9397 750 13961
Product data
Bit
Symbol
Reset
Access
DcErrorCode register: bit allocation
UNREAD
R
7
0
13.2.7 Acknowledge Setup (F4H)
13.3.1 Read Endpoint Error Code (R: A0H–AFH)
13.3 General commands
Table 95:
This command acknowledges to the host that a Setup packet was received. The
arrival of a Setup packet disables the Validate Buffer and Clear Buffer commands for
the control IN and OUT endpoints. The microprocessor needs to re-enable these
commands by sending an Acknowledge Setup command, see
Code (Hex): F4 — acknowledge set-up
Transaction — none
This command returns the status of the last transaction of the selected endpoint, as
stored in the DcErrorCode register. Each new transaction overwrites the previous
status information. The bit allocation of the DcErrorCode register is shown in
Table
Code (Hex): A0 to AF — read error code (control OUT, control IN, endpoint 1 to 14)
Transaction — read 1 word
Table 97:
DATA01
Bit
3
2
1
0
Bit
7
6
R
6
0
96.
DcEndpointStatusImage register: bit description
DcErrorCode register: bit description
Symbol
OVERWRITE
SETUPT
CPUBUF
-
Symbol
UNREAD
DATA01
reserved
R
5
0
Rev. 03 — 23 December 2004
Description
This bit is set by hardware, a logic 1 indicating that a new Setup
packet has overwritten the previous set-up information, before it
was acknowledged or before the endpoint was stalled. If writing
the set-up data has finished, this bit is cleared by a read action.
Firmware must check this bit before sending an Acknowledge
Setup command or stalling the endpoint. Upon reading a logic 1
the firmware must stop ongoing set-up actions and wait for a
new Setup packet.
A logic 1 indicates that the buffer contains a Setup packet.
This bit indicates which buffer is currently selected for CPU
access (0 = primary buffer, 1 = secondary buffer).
reserved
Description
A logic 1 indicates that a new event occurred before the
previous status was read.
This bit indicates the PID type of the last successfully received
or transmitted packet (0 = DATA0 PID, 1 = DATA1 PID).
R
4
0
USB single-chip host and device controller
R
3
0
ERROR[3:0]
R
2
0
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
…continued
ISP1161A1
Section
R
1
0
11.3.6.
RTOK
103 of 136
R
0
0