ISP1161A1BM ST-Ericsson Inc, ISP1161A1BM Datasheet - Page 98

• Manufacturer Part Number: ISP1161A1BM
• Description: IC USB HOST/DEVICE CTRLR 64-LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1161A1BM

• Controller Type: USB 2.0 Controller
• Interface: Parallel
• Voltage - Supply: 3.3V, 5V
• Current - Supply: 47mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-1163; ISP1161A1BM,557

Philips Semiconductors
Table 84:
9397 750 13961
Product data
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
DcInterruptEnable register: bit allocation
reserved
IEP14
IEP6
R/W
R/W
R/W
31
23
15
0
0
7
0
13.1.6 DcDMAConfiguration register (R/W: F1H/F0H)
SP_IEEOT
Code (Hex): C2/C3 — write/read DcInterruptEnable register
Transaction — write/read 2 words
Table 85:
This command defines the DMA configuration of the ISP1161A1’s DC and
enables/disables DMA transfers. The command accesses the DcDMAConfiguration
register, which consists of 2 bytes. The bit allocation is given in
will clear bit DMAEN (DMA disabled), all other bits remain unchanged.
Code (Hex): F0/F1 — write/read DMA Configuration
Transaction — write/read 1 word
Bit
31 to 24
23 to 10
9
8
7
6
5
4
3
2
1
0
IEP13
IEP5
R/W
R/W
R/W
30
22
14
0
0
6
0
DcInterruptEnable register: bit description
Symbol
-
IEP14 to IEP1 A logic 1 enables interrupts from the indicated endpoint.
IEP0IN
IEP0OUT
-
SP_IEEOT
IEPSOF
IESOF
IEEOT
IESUSP
IERESM
IERST
IEPSOF
IEP12
IEP4
R/W
R/W
R/W
29
21
13
0
0
5
0
Rev. 03 — 23 December 2004
IESOF
IEP11
Description
reserved; must write logic 0
A logic 1 enables interrupts from the control IN endpoint.
A logic 1 enables interrupts from the control OUT endpoint.
reserved
A logic 1 enables interrupt upon detection of a short packet.
A logic 1 enables 1 ms interrupts upon detection of
Pseudo SOF.
A logic 1 enables interrupt upon SOF detection.
A logic 1 enables interrupt upon EOT detection.
A logic 1 enables interrupt upon detection of ‘suspend’ state.
A logic 1 enables interrupt upon detection of a ‘resume’ state.
A logic 1 enables interrupt upon detection of a bus reset.
IEP3
R/W
R/W
R/W
28
20
12
0
0
4
0
reserved
R/W
00H
IEEOT
IEP10
USB single-chip host and device controller
IEP2
R/W
R/W
R/W
27
19
11
0
0
3
0
IESUSP
IEP9
IEP1
R/W
R/W
R/W
26
18
10
0
0
2
0
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
ISP1161A1
IERESM
IEP0IN
Table
IEP8
R/W
R/W
R/W
25
17
0
9
0
1
0
86. A bus reset
IEP0OUT
IERST
IEP7
R/W
R/W
R/W
97 of 136
24
16
0
8
0
0
0