ISP1161A1BM ST-Ericsson Inc, ISP1161A1BM Datasheet - Page 90

• Manufacturer Part Number: ISP1161A1BM
• Description: IC USB HOST/DEVICE CTRLR 64-LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1161A1BM

• Controller Type: USB 2.0 Controller
• Interface: Parallel
• Voltage - Supply: 3.3V, 5V
• Current - Supply: 47mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-1163; ISP1161A1BM,557

Philips Semiconductors
9397 750 13961
Product data
12.4.2 Isochronous endpoints
DcDMACounter register:
setting bit CNTREN in the DcDMAConfiguration register. The ISP1161A1 has a 16-bit
DcDMACounter register, which specifies the number of bytes to be transferred. When
DMA is enabled (DMAEN = 1), the internal DMA counter is loaded with the value from
the DcDMACounter register. When the internal counter completes the transfer as
programmed in the DcDMACounter, an EOT condition is generated and the DMA
operation stops.
Short packet:
before any DMA transfer takes place. When a short packet has been enabled as EOT
indicator (SHORTP = 1), the transfer size is determined by the presence of a short
packet in the data. This mechanism permits the use of a fully autonomous data
transfer protocol.
When reading from an OUT endpoint, reception of a short packet at an OUT token
will stop the DMA operation after transferring the data bytes of this packet.
Table 73:
[1]
A DMA transfer to/from an isochronous endpoint can be terminated by any of the
following conditions (bit names refer to the DcDMAConfiguration register, see
Table
Table 74:
EOT condition
EOT input
DcDMACounter register
Short packet
Bit DMAEN in
DcDMAConfiguration register
EOT condition
EOT input active
DMA Counter register zero
End-Of-Packet
•
•
•
•
An external End-Of-Transfer signal occurs on input EOT
The DMA transfer completes as programmed in the DcDMACounter register
(CNTREN = 1)
An End-Of-Packet (EOP) signal is detected
DMA operation is disabled by clearing bit DMAEN.
The DMA transfer stops. However, no interrupt is generated.
86):
Summary of EOT conditions for a bulk endpoint
Recommended EOT usage for isochronous endpoints
Normally, the transfer byte count must be set via a control endpoint
Rev. 03 — 23 December 2004
An EOT from the DcDMACounter register is enabled by
OUT endpoint
EOT is active
transfer completes as
programmed in the
DcDMACounter register
short packet is received and
transferred
DMAEN = 0
OUT endpoint
do not use
do not use
preferred
USB single-chip host and device controller
[1]
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
IN endpoint
EOT is active
transfer completes as
programmed in the
DcDMACounter register
counter reaches zero in the
middle of the buffer
DMAEN = 0
IN endpoint
preferred
preferred
do not use
ISP1161A1
[1]
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