ISP1161A1BM ST-Ericsson Inc, ISP1161A1BM Datasheet - Page 95

• Manufacturer Part Number: ISP1161A1BM
• Description: IC USB HOST/DEVICE CTRLR 64-LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1161A1BM

• Controller Type: USB 2.0 Controller
• Interface: Parallel
• Voltage - Supply: 3.3V, 5V
• Current - Supply: 47mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-1163; ISP1161A1BM,557

Philips Semiconductors
Table 80:
[1]
9397 750 13961
Product data
Bit
Symbol
Reset
Access
Unchanged by a bus reset.
DcMode register: bit allocation
DMAWD
R/W
0
7
[1]
13.1.3 DcMode register (R/W: B9H/B8H)
13.1.4 DcHardwareConfiguration register (R/W: BBH/BAH)
This command is used to access the ISP1161A1’s DcMode register, which consists
of 1 byte (for bit allocation: see
ignored.
The DcMode register controls the DMA bus width, resume and suspend modes,
interrupt activity and SoftConnect operation. It can be used to enable debug mode,
where all errors and Not Acknowledge (NAK) conditions will generate an interrupt.
Code (Hex): B8/B9 — write/read Mode register
Transaction — write/read 1 word
reserved
Table 81:
This command is used to access the DcHardwareConfiguration register, which
consists of 2 bytes. The first (lower) byte contains the device configuration and
control values, the second (upper) byte holds the clock control bits and the clock
division factor. The bit allocation is given in
of the programmed bit values.
Bit
7
6
5
4
3
2
1
0
R/W
6
0
DcMode register: bit description
Symbol
DMAWD
-
GOSUSP
-
INTENA
DBGMOD
-
SOFTCT
GOSUSP
R/W
5
0
Rev. 03 — 23 December 2004
reserved
Description
A logic 1 selects 16-bit DMA bus width (bus configuration
modes 0 and 2). A logic 0 selects 8-bit DMA bus width. Bus
reset value: unchanged.
reserved
Writing a logic 1 followed by a logic 0 will activate ‘suspend’
mode.
reserved
A logic 1 enables all DC interrupts. Bus reset value: unchanged;
for details, see
A logic 1 enables debug mode where all NAKs and errors will
generate an interrupt. A logic 0 selects normal operation, where
interrupts are generated on every ACK (bulk endpoints) or after
every data transfer (isochronous endpoints).
Bus reset value: unchanged.
reserved
A logic 1 enables SoftConnect (see
ignored if EXTPUL = 1 in the DcHardwareConfiguration register
(see
R/W
4
0
Table
Table
82). Bus reset value: unchanged.
79). In 16-bit bus mode the upper byte is
INTENA
USB single-chip host and device controller
R/W
0
Section
3
[1]
Table
8.6.3.
DBGMOD
82. A bus reset will not change any
R/W
0
2
[1]
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Section
ISP1161A1
reserved
R/W
0
1
[1]
7.5). This bit is
SOFTCT
R/W
94 of 136
0
0
[1]