PNX1501E,557 NXP Semiconductors, PNX1501E,557 Datasheet - Page 782

• Manufacturer Part Number: PNX1501E,557
• Description: IC MEDIA PROC 266MHZ 456-BGA
• Manufacturer: NXP Semiconductors

Specifications of PNX1501E,557

• Applications: Multimedia
• Core Processor: TriMedia
• Controller Series: Nexperia
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 61
• Voltage - Supply: 1.14 V ~ 1.26 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 456-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Type: -
• Ram Size: -
• Other names: 935274728557; PNX1501E; PNX1501E

Philips Semiconductors
Volume 1 of 1
4. Register Descriptions
Table 2: Register Summary
Table 3: PMAN (Hub) Arbiter Registers
PNX15XX_SER_3
Product data sheet
Offset
0x06 4000—41FC
0x06 4200—423C
0x06 4240—427C
0x06 4280—42BC
0x06 42C0—42FC
0x06 4300—431C
0x06 4320—43FC
0x06 4400—45FC
0x06 4600—463C
0x06 4640—467C
0x06 4680—46BC
0x06 46C0—46FC
0x06 4700—471C
0x06 4720—47FC
0x06 4800
0x06 4804
0x06 4808—48FC
0x06 4900
0x06 4904
0x06 4908—4FF8
0x06 4FFC
Bit
Arbiter Registers (Set A)
Offset 0x06 4000—41FC Entries of TDMA Timing Wheel (Set A)
31:10
9:8
7:5
4:0
Symbol
Reserved
R/W Grant
Reserved
Agent_ID
4.1 Register Table
Symbol
TDMA A
PRIORITY A
Reserved
FIRST Round Robin A
Reserved
LAST Round Robin A
Reserved
TDMA B
PRIORITY A
Reserved
FIRST Round Robin B
Reserved
LAST Round Robin B
Reserved
NR Entries A
NR Entries B
Reserved
Control
Status
Reserved
MODULE_ID
Acces
s
R
R/W
R
R/W
Value
0
0
0
0
Rev. 3 — 17 March 2006
Description
To ensure software backward compatibility, writes to unused or
reserved bits should be zero and reads must be ignored.
Grant on read, write or both
0x0 = grant independent whether it is a read or write
0x1, 0x2, 0x3 = reserved
To ensure software backward compatibility, writes to unused or
reserved bits should be zero and reads must be ignored.
ID of the agent that is identified by this entry (see
page 26-2
Description
128 entries of TDMA timing wheel for set A
16 entries of priority list for set A
16 entries of first round robin list for set A
8 entries of last round robin list for set A
128 entries of TDMA timing wheel for set B
16 entries of priority list for set B
16 entries of first round robin list for set B
8 entries of last round robin list for set B
Number of valid entries in arbitration lists for set A
Number of valid entries in arbitration lists for set B
Register to control operation mode of arbiter
Register to monitor operation mode of arbiter
Module ID and revision information
for IDs).
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Chapter 26: Memory Arbiter
PNX15xx Series
Table 1 on
26-7