PNX1501E,557 NXP Semiconductors, PNX1501E,557 Datasheet - Page 342

• Manufacturer Part Number: PNX1501E,557
• Description: IC MEDIA PROC 266MHZ 456-BGA
• Manufacturer: NXP Semiconductors

Specifications of PNX1501E,557

• Applications: Multimedia
• Core Processor: TriMedia
• Controller Series: Nexperia
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 61
• Voltage - Supply: 1.14 V ~ 1.26 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 456-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Type: -
• Ram Size: -
• Other names: 935274728557; PNX1501E; PNX1501E

Philips Semiconductors
Volume 1 of 1
Table 9: Register Description
PNX15XX_SER_3
Product data sheet
Bit
Offset 0x06 5120
31:4
3:0
Offset 0x06 5124
31:4
3:0
Offset 0x06 5128
31:4
3:0
Offset 0x06 512C
31:6
15:0
Arbitration Parameters
Offset 0x06 5180
31
30
29
28
27:18
Symbol
Unused
TRFC
Unused
TMRD
Unused
TCAS
Unused
RF_PERIOD
CPU_DMA_DECR
CPU_HRT_SRT_ENAB
LE
BLB_ENABLE
DYN_RATIOS
Reserved
DDR_TRFC
DDR_TMRD
DDR_TCAS
DDR_RF_PERIOD
ARB_CTL
Access Value
R
R/W
R
R/W
R
R/W
R
R/W
R/W
R/W
R/W
R/W
R
-
0xf
-
2
-
8
-
3515
1
0
0
0
-
Rev. 3 — 17 March 2006
Description
These bits should be ignored when read, and written as 0’s.
Auto refresh command period.
These bits should be ignored when read, and written as 0’s.
Load mode register command cycle time.
These bits should be ignored when read, and written as 0s.
CAS read latency, specified in halve cycles. I.e., a value of 0b0111
(7) represents a CAS delay of 3.5 cycles (7 halve cycles).
These bits should be ignored when read, and written as 0s.
Refresh period expressed in terms of cycles. Typically a refresh is
required at an average interval of 15.625 us. For a 100 MHz. device
this translates into a RF_PERIOD value of 1562. For a 200 MHz.
device this translates into a RF_PERIOD value of 3125.
‘0’: Do not decrement CPU counters when in a DMA_WINDOW.
‘1’: Do decrement CPU counters when in a DMA_WINDOW.
‘0’: Controller will interpret that DMA port contains only Hard Real
Time DMA requests.
‘1’: Controller will interpret that DMA port contains Hard Real Time
or Soft Real Time DMA requests.
‘0’: Disable Back Log Buffer
‘1’: Enable Back Log Buffer.
‘0’: Use Static Ratios. This means accounts are incremented by the
value (RATIO+ DDR burst size (in terms of cycles)) whenever a
CPU DDR burst is performed.
‘1’: Enable Dynamic Ratios. This means accounts are incremented
by the value RATIO every clock cycle that is spent on servicing a
CPU DDR burst. This feature also causes account not to decrement
during clock cycles that are spent on CPU DDR bursts.
These bits should be ignored when read, and written as 0s.
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Chapter 9: DDR Controller
PNX15xx Series
9-29