PNX1501E,557 NXP Semiconductors, PNX1501E,557 Datasheet - Page 131

• Manufacturer Part Number: PNX1501E,557
• Description: IC MEDIA PROC 266MHZ 456-BGA
• Manufacturer: NXP Semiconductors

Specifications of PNX1501E,557

• Applications: Multimedia
• Core Processor: TriMedia
• Controller Series: Nexperia
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 61
• Voltage - Supply: 1.14 V ~ 1.26 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 456-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Type: -
• Ram Size: -
• Other names: 935274728557; PNX1501E; PNX1501E

Philips Semiconductors
Volume 1 of 1
Table 8: Global Registers
PNX15XX_SER_3
Product data sheet
6
5
4:3
Bit
Symbol
VDO_MODE
VDO_MODE
Unused
…Continued
Acces
s
R/W
R/W
-
Value
0
0
-
Rev. 3 — 17 March 2006
Description
‘0’: No action
‘1’: When VDO_MODE[2:0] = 100, i.e. digital 24-bit YUV or RGB
video:
QVCP_DATA[15:12,9:2]
QVCP_DATA[29:22,19:16]
i.e. G[3:0], B[7:0]
i.e. R[7:0], G[7:4]
i.e. U[3:0], V[7:0]
i.e. Y[7:0], U[7:4]
All the other VDO pins are mapped as described below for
VDO_MODE[2:0] = 100.
This mode is typically used to interface with Video Encoders like the
Philips SAA7104 that require the video data to be presented on both
edges of the pixel clock. This mode allows to transfer the 24-bit data
over a 12-bit interface, VDO_D[16:5].
Note: The YUV mode does not match the SAA7104 expected
inputs. Use the RGB mode instead.
Note: This mode requires a 50/50 duty cycle clock. This can be
achieved by programming the QVCP PLL at twice the speed and
divide it by 2 by setting the P divider to 1, or use a times 4 or 8 as
described in
‘0’: No action
‘1’: When VDO_MODE[2:0] = 010, i.e. digital 16-bit YUV video:
QVCP_DATA[19:12] -> VDO_D[20:13] when VDO_CLK1=1
QVCP_DATA[9:2]
i.e. UV[7:0]
i.e. Y[7:0]
All the other VDO pins are mapped as described below for
VDO_MODE[2:0] = 010.
This mode is typically used to interface with Video Encoders like the
Philips SAA7104 that require the video data to be presented on both
edges of the pixel clock. This mode allows to transfer the 16-bit data
over an 8-bit interface, VDO_D[20:13].
Note: This mode requires a 50/50 duty cycle clock. This can be
achieved by programming the QVCP PLL at twice the speed and
divide it by 2 by setting the P divider to 1, or use a times 4 or 8 as
described in
To ensure software backward compatibility, writes to unused or
reserved bits should be zero and reads must be ignored.
Section PLL Settings page
Section PLL Settings page
-> VDO_D[20:13] when VDO_CLK1=0
-> VDO_D[20:13] when VDO_CLK1=0
-> VDO_D[20:13] when VDO_CLK1=1
Chapter 3: System On Chip Resources
-> VDO_D[16:5] when VDO_CLK1=1
-> VDO_D[16:5] when VDO_CLK1=0
-> VDO_D[16:5] when VDO_CLK1=1
-> VDO_D[16:5] when VDO_CLK1=1
-> VDO_D[16:5] when VDO_CLK1=0
-> VDO_D[16:5] when VDO_CLK1=0
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX15xx Series
5-9.
5-9.
3-22