PNX1501E,557 NXP Semiconductors, PNX1501E,557 Datasheet - Page 752

• Manufacturer Part Number: PNX1501E,557
• Description: IC MEDIA PROC 266MHZ 456-BGA
• Manufacturer: NXP Semiconductors

Specifications of PNX1501E,557

• Applications: Multimedia
• Core Processor: TriMedia
• Controller Series: Nexperia
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 61
• Voltage - Supply: 1.14 V ~ 1.26 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 456-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Type: -
• Ram Size: -
• Other names: 935274728557; PNX1501E; PNX1501E

Philips Semiconductors
Volume 1 of 1
PNX15XX_SER_3
Product data sheet
3.2 Debug Settings
Transfer of Data to TM3260 via JTAG
Poll control register to check if input buffer is empty or not and scan in data when it is
empty and set the ifull control bit to 1 triggering an interrupt. Note that scanning in any
instruction automatically scans out the 3 least significant bits (including the ifull or
ofull bit) of the selected TM_DBG_CTRL register.
Table 3: Transfer of Data In via JTAG
Figure 2
PNX15xx Series system and a simplified block diagram of the PNX15xx Series
processor. The JTAG Interface Module, shown separately in the diagram, may be a
PC add-on card such as PC-1149.1/100F Boundary Scan Controller Board or a
similar module connected to a PC serial or parallel port. The JTAG interface module
is necessary for PNX15xx Series systems that are not plugged into a PC. For PC-
hosted PNX15xx Series systems, the host based TM3260 debugger front-end can
communicate with the target resident debug monitor via the PCI bus.
Enhancements to the standard JTAG functionality include a handshake mechanism
for transferring data to and from a PNX15xx Series processor’s MMIO registers,
support for posting an interrupt, and resetting processor state.
Action
IR shift in SEL_IFULL_IN instruction
While TM_DBG_CTRL2.ifull = 1, scan in SEL_IFULL_IN instruction
DR scan 33 bits of register TM_DBG_IFULL_IN
TOTAL
Figure 2:
shows an overview of the JTAG access path from a host machine to a target
System with JTAG Access
TM3260
CPU
JTAG
Connector
Controller
JTAG board
Rev. 3 — 17 March 2006
(such as a PC)
Host Machine
JTAG TAP (TCK, TMS, TDI, TDO)
D$
I$
Internal System Bus
MCU
Peripherals
Connection
Serial or Parallel
Scan Chain connecting possibly
other chips on board
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
JTAG Interface
Chapter 24: TM3260 Debug
May be a PC plug-in board
PNX15xx Series
Main
(SDRAM)
Memory
Module
Number of
TCK Cycles
12
11+
38
61+ cycles
24-6