PNX1501E,557 NXP Semiconductors, PNX1501E,557 Datasheet - Page 11

• Manufacturer Part Number: PNX1501E,557
• Description: IC MEDIA PROC 266MHZ 456-BGA
• Manufacturer: NXP Semiconductors

Specifications of PNX1501E,557

• Applications: Multimedia
• Core Processor: TriMedia
• Controller Series: Nexperia
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 61
• Voltage - Supply: 1.14 V ~ 1.26 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 456-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Type: -
• Ram Size: -
• Other names: 935274728557; PNX1501E; PNX1501E

Philips Semiconductors
Volume 1 of 1
2.1.3
2.1.4
2.1.5
2.1.6
2.1.7
2.1.8
Chapter 26: Memory Arbiter
1.
1.1
2.
2.1
2.2
2.2.1
2.3
Chapter 27: Power Management
1.
1.1
1.1.1
Chapter 28: Pixel Formats
1.
2.
3.
3.1
3.2
3.3
3.4
3.5
3.5.1
Chapter 29: Endian Mode
1.
1.1
2.
2.1
3.
3.1
3.2
4.
4.1
4.2
4.3
4.4
4.5
Chapter 30: DCS Network
2.
PNX15XX_SER_3
Product data sheet
Introduction
Functional Description
Power Management Mechanisms
Introduction
Summary of Native Pixel Formats
Native Pixel Format Representation
Introduction
Functional Description
Endian Mode Theory
PNX15xx Series Endian Mode Architecture
Details
Functional Description
Bit Counter
Control Register
Status Decoder and Register
Input Filter
Address Register and Comparator
Data Shift Register
Features
Arbiter Features
ID Mapping
DCS Gate
Arbitration Algorithm
Clock Management
Essential Operating Infrastructure During
Powerdown
Indexed Formats
16-Bit Pixel-Packed Formats
32-Bit Pixel-Packed Formats
Packed YUV 4:2:2 Formats
Planar YUV 4:2:0 and YUV 4:2:2 Formats
Planar Variants
Features
Endian Mode System Block Diagram
Law 1: The “CPU Rule”
Law 2: The “DMA Convention Rule”
Global Endian Mode
Module Control
Module DMA
SIMD Programming Issues
Optional Endian Mode Override
29-7
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-3
27-1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-8
. . . . . . . . . . . . . . . . . . . . . . . . . . 28-6
. . . . . . . . . . . . . . . . . . . . . . . . . . 29-7
. . . . . . . . . . . . . . . . . . . . . . . . . 25-3
. . . . . . . . . . . . . . . . . . . . . . . . . 26-2
. . . . . . . . . . . . . . . . . . . . . . . . . 28-3
. . . . . . . . . . . . . . . . . . . . . . . 25-4
. . . . . . . . . . . . . . . . . . . . . . 27-1
. . . . . . . . . . . . . . . . . . . . . 26-3
. . . . . . . . . . . . . . . . . . . . . 29-7
. . . . . . . . . . . . . . . . . . . 29-4
. . . . . . . . . . . . . . . . . . . 29-4
. . . . . . . . . . . . . . . . . 26-1
. . . . . . . . . . . . . . . . . 29-2
. . . . . . . . . . . . . . . . . 30-1
. . . . . . . . . . . . . . . . 29-8
. . . . . . . . . . . . . . . 28-5
. . . . . . . . . . . . . . 25-3
. . . . . . . . . . . . . . 28-4
. . . . . . . . . . . . . . 28-4
. . . . . . . . . . . 29-8
. . . . . . . . . 25-3
. . . . . . . . 29-6
. . . . . . . 27-1
. . . . . . . 29-2
. . . . . . 28-2
Rev. 3 — 17 March 2006
. . . . 28-3
. . 28-6
2.1.9
2.1.10
3.
3.1
2.3.1
3.
3.1
3.2
4.
4.1
1.1.2
1.1.3
1.1.4
1.1.5
3.5.2
3.5.3
4.
5.
6.
7.
8.
5.
6.
6.1
6.2
6.2.1
6.2.2
6.3
6.4
6.5
6.6
7.
1.
2.1
2.2
Register Descriptions
Operation
Register Descriptions
Universal Converter
Alpha Value and Pixel Transparency
RGB and YUV Values
Image Storage Format
System Endian Mode
Example: Audio In—Programmer’s View
9
Implementation Details
Detailed Example
Introduction
Related Interrupts
Modes of Operation
Register Tables
Arbiter Startup Behavior
Clock Programming
Register Programming Guidelines
Register Table
Module Powerdown Sequence
Peripheral Module Wakeup Sequence
TM3260 Powerdown Modes
SDRAM Controller
Semi-Planar 10-Bit YUV 4:2:2 and 4:2:0 Formats
28-9
Packed 10-bit YUV 4:2:2 format
PMAN Network Endian Block Diagram
DMA Across a DTL Interface
DTL Data Ordering Rules
Address Invariant Data Ordering Rules
Data Transfers Across the DCS Network
DMA Across the MTL Bus
DTL-to-MTL Adapters
PCI Interface
Error Generation
Interrupt Generation
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-6
PNX15xx Series
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-1
. . . . . . . . . . . . . . . . . . . . . . . . . . . 29-14
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
. . . . . . . . . . . . . . . . . . . . . . . . . . . 26-7
. . . . . . . . . . . . . . . . . . . . . . . . . . 25-8
. . . . . . . . . . . . . . . . . . . . . . . . . 30-2
. . . . . . . . . . . . . . . . . . . . . . . . 25-4
. . . . . . . . . . . . . . . . . . . . . . . . 27-3
. . . . . . . . . . . . . . . . . . . . . . 29-15
. . . . . . . . . . . . . . . . . . . . . . 25-4
. . . . . . . . . . . . . . . . . . . . . . 26-6
. . . . . . . . . . . . . . . . . . . . . . 30-2
. . . . . . . . . . . . . . . . . . . . 28-10
. . . . . . . . . . . . . . . . . . . . 29-14
. . . . . . . . . . . . . . . . . . . 25-7
. . . . . . . . . . . . . . . . . . . 26-6
. . . . . . . . . . . . . . . . . . . 26-7
. . . . . . . . . . . . . . . . . . 28-11
. . . . . . . . . . . . . . . . . . 28-12
. . . . . . . . . . . . . . . . . 28-11
. . . . . . . . . . . . . . . . 29-10
. . . . . . . . . . . . . . . . 29-11
. . . . . . . . . . . . . . . . 29-13
. . . . . . . . . . . . . . . 27-2
. . . . . . . . . . . . . 29-11
. . . . . . . . . . . . . 27-1
. . . . . . . . . . . 28-10
. . . . . . . . . . 26-6
. . . . . . 27-2
. . . . . 29-10
. . . . 29-12
. . . 28-11
. . . 29-12
29-
-11