PNX1501E NXP Semiconductors, PNX1501E Datasheet
PNX1501E
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PNX1501E Summary of contents
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PNX15xx Series Data Book Volume Connected Media Processor Rev. 2 — 1 December 2004 ...
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Philips Semiconductors Volume Table of Contents Chapter 1: Integrated Circuit Data 1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . ...
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Philips Semiconductors Volume 10.1.2 timestamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22 10.1.3 event sequence ...
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Philips Semiconductors Volume Chapter 6: Boot Module 1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Philips Semiconductors Volume 2.1 Start and Warm Start . . . . . . . . . . . . . . . . . . . . . . 9-2 2.1.1 The Start Mode . . ...
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Philips Semiconductors Volume 3.1 MMIO and Task Based Programming 3.2 Setup Order for the QVCP 3.2.1 Shadow Registers . . . . . . . . . . . . . . . . . . . ...
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Philips Semiconductors Volume Chapter 14: FGPI: Fast General Purpose Interface 1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Philips Semiconductors Volume Register Descriptions . . . . . . . . . . . . . . . . . 16-15 Chapter 17: SPDIF Output 1. Introduction . . . . . . . ...
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Philips Semiconductors Volume Chapter 20: 2D Drawing Engine 1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Philips Semiconductors Volume 3.3 Pattern Matching Join Register 4. Descriptor and Status Formats 4.1 Receive Descriptors and Status 4.2 Transmit Descriptors and Status 5. LAN100 Functions . . . . . . . . . . . ...
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Philips Semiconductors Volume 2.1.3 Bit Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-3 ...
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Philips Semiconductors Volume 2.3 Programmable Timeout . . . . . . . . . . . . . . . . . . . 30-2 2.3.1 Arbitration . . . . . . . . . ...
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Philips Semiconductors Volume 12NC 9397 750 14321 Product data sheet © Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved. Rev. 2 — 1 December 2004 PNX15xx Series -13 ...
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Philips Semiconductors Volume Chapter 1: Integrated Circuit Data Figure 1: Application Diagram of the Crystal Oscillator Figure 2: SSTL_2 Test Load Condition Figure 3: SSTL_2 Receiver Signal Conditions Figure 4: BPX2T14MCP Test Load Condition Figure 5: BPTS1CHP ...
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Philips Semiconductors Volume Figure 7: TM3260, DDR and QVCP clocks Figure 8: QVCP_PROC Clock . . . . . . . . . . . . . . . . . . . . . . . ...
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Philips Semiconductors Volume Chapter 9: DDR Controller Figure 1: The two MTL Ports of the DDR SDRAM Controller Figure 2: Arbitration in the DDR Controller Figure 3: CPU account . . . . . . . . ...
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Philips Semiconductors Volume Figure 11: Double Buffer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Philips Semiconductors Volume Figure 6: SPDIF Input Oversampling Clock Generation Figure 7: Lock/Unlock Processing for SPDIF Input Figure 8: SPDIF Input Consumer interface Figure 9: SPDIF Input MMIO Registers ( Figure 10: SPDIF Input MMIO ...
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Philips Semiconductors Volume Chapter 26: Memory Arbiter Figure 1: Arbitration Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Philips Semiconductors Volume Chapter 1: Integrated Circuit Data Table 1: PNX1500 I/O Types . . . . . . . . . . . . . . . . . . . . . . . . ...
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Philips Semiconductors Volume Chapter 3: System On Chip Resources Table 1: SYSTEM Registers . . . . . . . . . . . . . . . . . . . . . . . . ...
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Philips Semiconductors Volume Table 9: PCI Configuration Registers Chapter 8: General Purpose Input Output Pins Table 1: GPIO Pin List . . . . . . . . . . . . . . . . . ...
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Philips Semiconductors Volume Table 11: Resource-Layer Assignment for Pool Resource Table 12: Programming Values for Supported PNX15xx Series Output Formats Table 13: LINT programming . . . . . . . . . . . . . ...
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Philips Semiconductors Volume Table 4: Example Setup For SAA7366 Table 5: Operating Modes and Memory Formats Table 6: Endian Ordering of Audio Data in Main Memory Table 7: Audio In Data Bus Arbiter Latency Requirement Examples — ...
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Philips Semiconductors Volume Table 16: Destination Stride . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Philips Semiconductors Volume Chapter 24: TM3260 Debug Table 1: JTAG TM3260 Instruction Encoding Table 2: JTAG Instruction Encoding Table 3: Transfer of Data In via JTAG Table 4: Register Summary . . . . . . . ...
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Chapter 1: Integrated Circuit Data PNX15xx Series Data Book – Volume Rev. 2 — 1 December 2004 1. Introduction The PNX1500 Media Processor Series is a complete Audio/Video/Graphics system on a chip that contains a high-performance 32-bit ...
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Philips Semiconductors Volume PNX1500 uses different I/Os depending on the type of the interface, e.g. PCI, or electrical characteristics needed for the functionality, e.g. a clock signal requires sharper edges than a regular signal. The following table ...
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Philips Semiconductors Volume • Any I/O or I/OD signal of the XIO bus must be pulled-up if they are not used. • GPIO[11:8] must be pulled-up or down. The following pull-down or none (column ‘P’). Remark: The ...
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Philips Semiconductors Volume Table 4: PNX1500 Interface BGA Pad Pin Name Ball Type PCI_SYS_CLK E25 BPX2T14MCP Miscellaneous System Interface POR_IN_N A11 BPT3MCHT5V RESET_IN_N C7 BPT3MCHT5V SYS_RST_OUT_N D10 BPX2T14MCP RESERVED AB23 BPT3MCHDT5V Main Memory Interface (DDR SDRAM controller) ...
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Philips Semiconductors Volume Table 4: PNX1500 Interface BGA Pad Pin Name Ball Type MM_BA1 P4 MM_BA0 R4 MM_ADDR12 K4 MM_ADDR11 K3 MM_ADDR10 T4 MM_ADDR09 L4 MM_ADDR08 N4 MM_ADDR07 P1 MM_ADDR06 R1 MM_ADDR05 T1 MM_ADDR04 U3 MM_ADDR03 U4 ...
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Philips Semiconductors Volume Table 4: PNX1500 Interface BGA Pad Pin Name Ball Type MM_DATA31 AD2 MM_DATA30 AD1 MM_DATA29 AB2 MM_DATA28 AC1 MM_DATA27 AB1 MM_DATA26 AA2 MM_DATA25 AA1 MM_DATA24 W2 MM_DATA23 W4 MM_DATA22 Y3 MM_DATA21 Y4 MM_DATA20 AA3 ...
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Philips Semiconductors Volume Table 4: PNX1500 Interface BGA Pad Pin Name Ball Type PCI_AD31 H24 PCI_AD30 G26 PCI_AD29 J23 PCI_AD28 H25 PCI_AD27 H26 PCI_AD26 K23 PCI_AD25 J25 PCI_AD24 J26 PCI_AD23 L23 PCI_AD22 L24 PCI_AD21 L25 PCI_AD20 L26 ...
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Philips Semiconductors Volume Table 4: PNX1500 Interface BGA Pad Pin Name Ball Type PCI_TRDY_N N24 PCI_STOP_N P24 PCI_IDSEL K26 PCI_DEVSEL_N P26 PCI_REQ_N F23 PCI_GNT_N D24 PCI_REQ_A_N G23 PCI_GNT_A_N D25 PCI_REQ_B_N H23 PCI_GNT_B_N D26 PCI_PERR_N P23 PCI_SERR_N R25 ...
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Philips Semiconductors Volume Table 4: PNX1500 Interface BGA Pad Pin Name Ball Type PCI_INTA_N D23 Additional XIO bus signals to the regular PCI bus signals to implement Flash, IDE drive interface and M68k System Buses. XIO_D15 AA25 ...
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Philips Semiconductors Volume Table 4: PNX1500 Interface BGA Pad Pin Name Ball Type VDI_D31 AC14 VDI_D30 AF12 VDI_D29 AE12 VDI_D28 AF11 VDI_D27 AC13 VDI_D26 AD11 VDI_D25 AF10 VDI_D24 AE10 VDI_D23 AF9 VDI_D22 AC12 VDI_D21 AD10 VDI_D20 AE9 ...
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Philips Semiconductors Volume Table 4: PNX1500 Interface BGA Pad Pin Name Ball Type VDI_CLK2 AC6 BPX2T14MCP VDI_V2 AE1 Video/Data Out Pin Group The video mode provides ITU656 8-, 10- and 16-bit outputs, or digital 24-/30-bit HD YUV ...
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Philips Semiconductors Volume Table 4: PNX1500 Interface BGA Pad Pin Name Ball Type VDO_D31 C26 VDO_D30 E26 VDO_D29 D20 VDO_D28 F24 VDO_D27 F25 VDO_D26 F26 VDO_D25 G24 VDO_D24 G25 VDO_D23 D19 VDO_D22 C25 VDO_D21 B26 VDO_D20 D22 ...
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Philips Semiconductors Volume Table 4: PNX1500 Interface BGA Pad Pin Name Ball Type VDO_CLK2 B19 BPX2T14MCP VDO_AUX E24 FGPO_REC_SYNC C17 FGPO_BUF_SYNC A18 Octal Audio In (audio in always acts as receiver, but can be set as master ...
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Philips Semiconductors Volume Table 4: PNX1500 Interface BGA Pad Pin Name Ball Type AI_WS AD21 AI_SD3 AD22 BPT3MCHDT5V AI_SD2 AC17 BPT3MCHDT5V AI_SD1 AF24 BPT3MCHDT5V AI_SD0 AE23 BPT3MCHDT5V Octal Audio Out (audio out always acts as sender, but ...
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Philips Semiconductors Volume Table 4: PNX1500 Interface BGA Pad Pin Name Ball Type AO_WS AE20 AO_SD3 AF21 AO_SD2 AF20 AO_SD1 AE19 AO_SD0 AF19 SPDIF interface SPDI A6 BPT3MCHDT5V SPDO AF22 BPX2T14MCP 10/100 LAN interface (MII) LAN_CLK AF18 ...
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Philips Semiconductors Volume Table 4: PNX1500 Interface BGA Pad Pin Name Ball Type LAN_RX_CLK/ AF16 LAN_REF_CLK LAN_RXD3 AD17 LAN_RXD2 AD16 LAN_RXD1 AF17 LAN_RXD0 AE16 LAN_RX_DV AE15 LAN_RX_ER AD15 LAN_MDIO AC26 LAN_MDC AC25 Interface IIC_SDA ...
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Philips Semiconductors Volume Table 4: PNX1500 Interface BGA Pad Pin Name Ball Type GPIO06/CLOCK06 B9 GPIO05/CLOCK05 A8 BPX2T14MCP GPIO04/CLOCK04 A7 GPIO03/CLOCK03/ A4 BOOT_MODE03 GPIO02/CLOCK02/ A3 BOOT_MODE02 - GPIO01/CLOCK01/ B3 BOOT_MODE01 - GPIO00/CLOCK00/ B4 BOOT_MODE00 - JTAG Interface ...
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Philips Semiconductors Volume 2.3.1 Power Pin List Table 5: Power Pin List Digital Ground 3.3-V VSS VCCP T11 N11 V5 AB7 T12 N12 U5 AB8 T13 N13 T2 AB13 T14 N14 M3 AB14 T15 N15 H3 P22 ...
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Philips Semiconductors Volume 2.3.2 Pin Reference Voltage Table 6: Pin Reference Voltage 3.3 V Input and/or Output 5.0 V Input Tolerant 3.3 V Input and/or Output POR_IN_N PCI_AD31 PCI_SYS_CLK RESET_IN_N PCI_AD30 SYS_RST_OUT_N PCI_CLK PCI_AD29 VDO_CLK1 PCI_C/BE03 PCI_AD28 ...
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Philips Semiconductors Volume operation above the operation range described in maximum ratings may significantly reduce the reliability of the PNX1500. Table 7: Absolute Maximum Ratings Symbol Description V 3.3 V I/O supply voltage CCP V 2.5 V ...
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Philips Semiconductors Volume Power Supply and Operating Speeds Table 9: Maximum Operating Speeds Based on the VDD Power Supply for the PNX1501 Core Supply TM3260 MMI MMIO (V) (MHz) (MHz) (MHz) 1.2 266 200 157 Table ...
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Philips Semiconductors Volume • Turn off the unused modules. After reset, the modules are clocked with a 27 MHz clock (input crystal clock, XTAL_IN). Turning off the clocks of the unused modules significantly reduces the power consumption. ...
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Philips Semiconductors Volume 7.1 Input Crystal Specification Table 15: Specification of HC-49U 27.00000 MHZ Crystal Frequency Temperature range Capacitive load (CL) Frequency accuracy (all included: temperature, aging, frequency Series resonance resistor Shunt capacitance ...
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Philips Semiconductors Volume Table 16: SSTL_2 AC/DC Characteristics Symbol Parameter R Series Output Resistance High/Low level output state SSTL T Slew rate, SLEW ( )/dt IH-AC IL-AC C Input pin capacitance IN [16-1] [16-2] Figure ...
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Philips Semiconductors Volume 7.3 BPX2T14MCP Type I/O Circuit Table 17: BPX2T14MCP Characteristics Symbol Parameter V Output High Voltage OH V Output Low Voltage Input High Voltage IHT V DC Input Low Voltage ILT V ...
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Philips Semiconductors Volume 7.4 BPTS1CHP and BPTS1CP Type I/O Circuit Table 18: BPTS1CHP and BPTS1CP Characteristics Symbol Parameter V Output High Voltage OH V Output Low Voltage Input High Voltage IHT V DC Input ...
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Philips Semiconductors Volume 7.5 BPTS3CHP Type I/O Circuit Table 19: BPTS3CHP Characteristics Symbol Parameter V Output High Voltage OH V Output Low Voltage Input High Voltage IHT V DC Input Low Voltage ILT V ...
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Philips Semiconductors Volume 7.6 IPCHP and IPCP Type I/O Circuit Table 20: IPCHP and IPCP Characteristics Symbol Parameter V DC Input High Voltage IHT V DC Input Low Voltage ILT V DC Input High Voltage IH V ...
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Philips Semiconductors Volume 7.8 IIC3M4SDAT5V and IIC3M4SCLT5V type I/O circuit Table 22: IIC3M4SDAT5V and IIC3M4SCLT5V Characteristics Symbol Parameter V Input High Voltage IH V Input Low Voltage IL V Input Schmitt trigger Hysteresis HYS V Output Low ...
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Philips Semiconductors Volume 8.1 Reset Figure 9: Table 24: Reset Timing Symbol Parameter T Reset active time after power and clock stable LOWP T Reset active after POR_IN_N is pulled high HOLD T Reset active time after ...
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Philips Semiconductors Volume Table 25: DDR DRAM Interface Timing Symbol Parameter T Maximum input skew supported iskew-dqs (when reading from DDR SDRAM) T Input setup time for MM_DQ is-dq (when reading from DDR SDRAM) T Input hold ...
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Philips Semiconductors Volume [26-7] Figure 10: PCI Output and Input Timing Measurement Conditions Figure 11: PCI T 12NC 9397 750 14321 Product data sheet 6. For the purpose of Active/Float timing measurements, the Hi-Z or ‘off’ state ...
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Philips Semiconductors Volume 8.4 QVCP, LCD and FGPO Interfaces Table 27: QVCP, LCD and FGPO Timing With Internal Clock Generation Symbol Parameter F VDO_CLK1 frequency QVCP F VDO_CLK2 frequency FGPO T Clock to VDO_D[33:0] and VDO_AUX CLK-DV ...
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Philips Semiconductors Volume [28-4] [28-5] 8.5 VIP and FGPI Interfaces Table 29: VIP and FGPI Timing Symbol Parameter F VDI_CLK1 frequency VIP F VDI_CLK2 frequency FGPI T Input setup time SU-CLK T Input hold time H-CLK [29-1] ...
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Philips Semiconductors Volume [30-4] Figure 14: LAN 10/100 I/O Timing in MII Mode 8.7 10/100 LAN In RMII Mode Table 31: 10/100 LAN RMII Timing Symbol Parameter F LAN_CLK frequency LAN_CLK F LAN_TX_CLK and LAN_RX_CLK frequency CLK ...
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Philips Semiconductors Volume [31-4] Figure 15: LAN 10/100 I/O Timing in RMII Mode 8.8 Audio Input Interface Table 32: Audio Input Timing Symbol Parameter F Audio Input oversampling frequency OSCLK F Audio Input frequency AI_CLK T Clock ...
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Philips Semiconductors Volume See timing measurement conditions Figure 16: Audio Input I/O Timing 8.9 Audio Output Interface Table 33: Audio Output Timing Symbol Parameter F Audio Output oversampling frequency OSCLK F Audio Output frequency AO_CLK T ...
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Philips Semiconductors Volume See timing measurement conditions Figure 17: Audio Output I/O Timing 8.10 SPDIF I/O Interface Table 34: SPDIF I/O Timing Symbol Parameter T Data/Clock Output High Time HIGH T Data/Clock Output Low Time LOW ...
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Philips Semiconductors Volume 8. I/O Interface 2 Table 35 I/O Timing Symbol Parameter f SCL clock frequency SCL T Bus free time BUF T Start condition set up time SU-STA T Start ...
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Philips Semiconductors Volume Figure 20: I 8.12 GPIO Interface Table 36: GPIO Timing Symbol Parameter F GPIO sampling/pattern generation CLOCK frequency CLOCK T GPIO[6:0] CLOCK to DATA valid for GPIO[15:0] pins CLK-DV1 T GPIO[6:0] CLOCK to DATA ...
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Philips Semiconductors Volume See timing measurement conditions Figure 21: Audio Output I/O Timing 8.13 JTAG Interface Table 37: JTAG Timing Symbol Parameter F Boundary scan frequency BSCAN F JTAG frequency JTAG T Falling edge of the ...
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Philips Semiconductors Volume Package Outline Latest information may be found at http://www.semiconductors.philips.com/package/SOT795-1.html#footprint BGA456: plastic ball grid array package; 456 balls; body 1.75 mm ball A1 index area ...
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Philips Semiconductors Volume 10. Board Design Guidelines The following sections discuss the fundamentals of board design for the PNX1500 system. The intent is to give general guidelines on the subject, not the complete in depth coverage. A ...
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Philips Semiconductors Volume 10.2 Analog Supplies 10.2.1 The 3.3 V Analog Supply The entire analog ground/supply is kept free-floating on the PCB. Quiet VCCA for the PLL subsystem should be supplied from VCCP through a 18 series ...
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Philips Semiconductors Volume Figure 26: Digital VDD Power Supply to Analog VDDA/VSSA_1.2 Power Supply Filter 10.3 DDR SDRAM interface Designing a proper DDR SDRAM interface with the PNX1500 system that guarantees correct signal integrity and timing margins ...
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Philips Semiconductors Volume The ball assignment implies that the two outside rows of balls are routed on a different board layer than the next two rows of balls. This is recommended to reduce the skew. The DQS ...
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... MHz 1.2-V PNX1502E 12NC 9352 747 44557 300 MHz 1.3-V PNX1500E/G 12NC 9352 777 46557 240 MHz 1.2-V PNX1501E/G 12NC 9352 777 47557 266 MHz 1.2-V PNX1502E/G 12NC 9352 777 48557 300 MHz 1.3-V 12NC 9397 750 14321 ...
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Philips Semiconductors Volume 12NC 9397 750 14321 Product data sheet Chapter 1: Integrated Circuit Data © Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved. Rev. 2 — 1 December 2004 PNX15xx Series 1-48 ...
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Chapter 2: Overview PNX15xx Series Data Book – Volume Rev. 2 — 1 December 2004 1. Introduction The PNX15xx Series Media Processor is a complete Audio/Video/Graphics system on a chip that contains a high-performance 32-bit VLIW processor, ...
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Philips Semiconductors Volume Processing functions are those that modify an existing data structure and prepare that structure for display functions. Display functions take the processed data structures from memory and generate the appropriate output stream ...
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Philips Semiconductors Volume Table 1: Partitioning of Functions to Resources function image scaling video format conversions, including color space conversion histogram correction, black stretch, luminance sharpening (LTI, CDS, HDP), color features (green enhancement, skin tone correction, blue ...
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Philips Semiconductors Volume • 2-layer compositing video output, with integrated scaling and video improvement processing, supporting W-XGA TFTs, 1280 x 768 60 Hz, HD video 1920 x 1080 Mpix/s. ...
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Philips Semiconductors Volume PNX15xx Series Functional Block Diagram Figure 1 component is further explained in this chapter and later more detailed with a dedicated chapter 200 MHz (i.e 400 MHz data rate), 16- or ...
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Philips Semiconductors Volume System Resources 3.1 System Reset The PNX15xx Series includes a system reset module. This reset module provides a synchronous reset to internal PNX15xx Series logic and a reset output pin for initialization of ...
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Philips Semiconductors Volume The scripted boot, in combination with an appropriately programmed I allows the PNX15xx Series to boot in many ways. A stand-alone PNX15xx Series system is able to reliably update its own Flash boot image, ...
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Philips Semiconductors Volume – – – After wake-up from sleep mode, the TM3260 CPU can examine the tentative wake-up attempt, and if the wake-up is genuine, bring the system back to full operational mode. In addition, the ...
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Philips Semiconductors Volume System Memory 4.1 MMI - Main Memory Interface PNX15xx Series has an unified memory system for the PNX15xx Series CPU and all of its modules. This memory is also visible from any PCI ...
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Philips Semiconductors Volume PNX15xx Series provides 5 chip selects, one of which is intended for a Flash device. Address range, and wait states for a Flash device are programmable. The TM3260 can execute or read from direct ...
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Philips Semiconductors Volume image stream, MPEG-2 or MPEG-4 decode. The processor is also capable of doing all audio and video compression, decompression and processing necessary for bi- directional video conferencing. The TM3260 is responsible for all media ...
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Philips Semiconductors Volume Table 4: TM3260 Characteristics TM3260 VLIW CPU Features System Interface The TM3260 runs asynchronously with respect to system DRAM, and can operate at a frequency lower than system DRAM to save power, or higher ...
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Philips Semiconductors Volume • The Memory Based Scaler supports conversion from arbitrary pixel formats to any native format during the anti-flicker filtering operation. This operation is usually required on graphics images anyway, hence no extra passes are ...
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Philips Semiconductors Volume 7.2 Video Input Processor The Video Input Processor (VIP) handles incoming digital video and processes it for use by other components of the PNX15xx Series. VIP provides 10-bit accurate processing. The VIP provides the ...
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Philips Semiconductors Volume • edge detect/correct on an input frame that has been software de-interlaced (this provides future capabilities in case we develop a better core de-interlacer than 3- field majority select) • horizontal & vertical scaling ...
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Philips Semiconductors Volume – – – – – – – – QVCP supports the semi-planar YUV formats for one layer. Both layers support only indexed, RGB and packed YUV formats. QVCP does not support planar video formats. ...
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Philips Semiconductors Volume QVCP shares its allocated pins with the FGPO module through an output router. Refer to allocation. 7.5.1 External Video Improvement Post Processing The PNX15xx Series has a ‘VDO_AUX’ output pin that can be set ...
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Philips Semiconductors Volume one of the originally received compressed audio programs (5.1 channel AC-3, multi-channel MPEG audio, multi-channel AAC). Sample rate of transmitted audio is set by software, allowing perfect synchronization to any time reference in the ...
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Philips Semiconductors Volume The operating modes of the video/data input router are set by the VDI_MODE MMIO register. A subset of the operating modes are presented in 656 digital video source with streaming data inputs. A complete ...
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Philips Semiconductors Volume • Broadcast of messages more receiving PNX15xx Series’s. • Message or unstructured data transmission is in 8-, 16- or 32-bit parallel format, with data rates up to 100 MHz, providing an ...
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Philips Semiconductors Volume • 8-, 16- or 32-bit message passing between PNX15xx Series’s. Messages length are received and written to memory. Upon completion, an interrupt is generated, and the FGPI switches ...
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Philips Semiconductors Volume 10.1.1 software I/O Each GPIO pin is a tri-state pin that can be individually enabled, disabled, written or read. Pins are grouped in groups of 16 and signals within a group can be simultaneously ...
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Philips Semiconductors Volume The GPIO module has a total of 4 complex signal analysis/signal synthesis resources capable of sampling or timestamped list generation/creation. 10.1.4 GPIO pin reset value Dedicated GPIO pins come in two types: • 50% ...
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Philips Semiconductors Volume 10.3.1 PCI Capabilities PNX15xx Series complies with Revision 2.2 of the PCI bus specification, and operates as a 32-bit PCI master/target MHz. PNX15xx Series as PCI master allows TM3260 to generate ...
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Philips Semiconductors Volume The peripheral interface derives 24 of the 26 address wires and 8 out of the 16 data wires from the PCI AD[31:0] pins. The remaining pins are XIO specific and non PCI shared. An ...
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Philips Semiconductors Volume Table 9: PCI/XIO-16 Bus Interface Unit Capabilities External Device Device Type DOCSIS devices external SRAM, 8- and 16-bit wide ROM, EEPROM external DRAM not supported external Motorola not supported style masters external 8/16-bit not ...
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Philips Semiconductors Volume PNX15xx Series always starts in a fixed endian mode which is determined by the boot script. There is a system provision for TM3260 software to reset and restart the TM3260 in the opposite endian ...
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Philips Semiconductors Volume 12NC 9397 750 14321 Product data sheet © Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved. Rev. 2 — 1 December 2004 PNX15xx Series Chapter 2: Overview 2-28 ...
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Chapter 3: System On Chip Resources PNX15xx Series Data Book – Volume Rev. 2 — 1 December 2004 1. Introduction This chapter presents information on the PNX15xx Series System On-Chip (SOC) and its MMIO registers. Further details ...
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Philips Semiconductors Volume Before going into the details of the three different views the following generic rules should be noted: • The three views must be consistent. For example not allowed to have a different ...
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Philips Semiconductors Volume Remark: Partial 32-bit load or stores from a PCI master to an MMIO register is not supported. Therefore byte of 16-bit half-word accesses are not supported. 2.2 The CPU View The TM3260 CPU supports ...
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Philips Semiconductors Volume Remark: If the value 0x0000,0000 is stored into TM32_APERT1_HI, this value is understood as 0x1,0000,0000. 2.3 The DCS View Or The System View TM3260 0x1 0000 0000 inaccessible 2MB MMIO Aperture MMIO_BASE/base_14 inaccessible TM32_APERT1_HI ...
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Philips Semiconductors Volume the program phase where it is planned to be used). This creates random addresses that can target the APERT1 aperture. Therefore the load may generate a transaction on the PCI bus ...
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Philips Semiconductors Volume 2.4.1 DCS DRAM Aperture Control MMIO Registers Table 1: SYSTEM Registers Acces Bit Symbol s DCS DRAM Aperture Control Registers Offset 0x06 3200 DCS_DRAM_LO 31:16 DCS_DRAM_LO R/W 15:0 Unused - Offset 0x06 3204 DCS_DRAM_HI ...
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Philips Semiconductors Volume Other than the PCI module, only the TM3260 CPU can emit requests to the PCI bus, i.e. none of the other PNX15xx Series modules can do so. Only the TM3260 CPU and external PCI ...
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Philips Semiconductors Volume 3.3 System Module MMIO registers Table 2: SYSTEM REGISTERS Acces Bit Symbol s System Module Registers Offset 0x06 3FF4 GLB_REG_POWER_DOWN 31 POWER_DOWN R/W 30:0 Unused - Offset 0x06 3FFC GLB_REG_MOD _ID 31:16 MODULE_ID R ...
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Philips Semiconductors Volume 4.1 System Endian Mode MMIO registers Table 3: SYSTEM REGISTERS Acces Bit Symbol s System Endian Mode Registers Offset 0x06 3014 SYS_ENDIANMODE 31:1 Unused - 0 BIG_ENDIAN R/W 5. System Semaphores PNX15xx Series has ...
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Philips Semiconductors Volume • PCI configspace PERSONALITY entry. Each PNX15xx Series receives a 16-bit PERSONALITY value from the EEPROM during boot. This PERSONALITY register is located at offset 0x40 in configuration space system, some ...
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Philips Semiconductors Volume 5.5 Semaphore MMIO Registers Table 4: Semaphore MMIO Registers Acces Bits Symbol s Semaphore Registers Offset 0x06 3800 SEMAPHORE0 31:12 Unused - 11:0 SEMAPHORE0 R/W Offset 0x06 3804 SEMAPHORE1 31:0 SEMAPHORE1 R/W Offset 0x06 ...
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Philips Semiconductors Volume Table 4: Semaphore MMIO Registers Acces Bits Symbol s 31:0 SEMAPHORE14 R/W Offset 0x06 383C SEMAPHORE15 31:0 SEMAPHORE15 R/W 6. System Related Information for TM3260 This section contains information on how the internal TM3260 ...
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Philips Semiconductors Volume Table 5: Interrupt Source Assignments SOURCE SOURCE NAME NUMBER TIMER3 7 SYSTIMER 8 VIP 9 QVCP SPDI 13 SPDO 14 ETHERNET 15 I2C 16 TMDBG 17 FGPI 18 FGPO ...
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Philips Semiconductors Volume Table 5: Interrupt Source Assignments SOURCE SOURCE NAME NUMBER DCS 60 MMI 61 Reserved 62...63 6.2 Timers The TM3260 CPU contains four programmable timer/counters, all with the same function. The first three (TIMER1, TIMER2, ...
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Philips Semiconductors Volume 6.3 System Parameters for TM3260 Few more control parameters are available to tune the use of TM3260 and PNX15xx Series. The MMIO register layout and offsets are described in • The CPU apertures (DRAM ...
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Philips Semiconductors Volume 6.3.1 TM3260 Table 7: TM3260 System Parameters MMIO Registers Acces Bit Symbol s System Module Registers Offset 0x06 3700 TM32_CONTROL 31:4 Unused - 3 TM32_APERT_MODIFI R/W ABLE 2 TM32_LS_DBLLINE R/W 1 TM32_IFU_DBLLINE R/W 0 ...
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Philips Semiconductors Volume Section 7.1 VDI_MODE and VDO_MODE MMIO registers. page 2-19 7.1 MMIO Registers for the Input/Output Video/Data Router In the following tables • The X associated with a bit value means ‘do not care’. • ...
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Philips Semiconductors Volume Table 8: Global Registers Acces Bit Symbol s Input and Output Control Registers Offset 0x06 3000 VDI_MODE 31:8 Unused - 7 VDI_MODE_7 R/W 6:5 Unused - 12NC 9397 750 14321 Product data sheet Chapter ...
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Philips Semiconductors Volume Table 8: Global Registers …Continued Acces Bit Symbol s 4:3 VDI_MODE[4:3] R/W 2 VDI_MODE[2] is unused - 1:0 VDI_MODE[1:0] R/W 12NC 9397 750 14321 Product data sheet Chapter 3: System On Chip Resources Value ...
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Philips Semiconductors Volume Table 8: Global Registers …Continued Acces Bit Symbol s 4:3 VDI_MODE[4:3] R/W 2 VDI_MODE[2] is unused - 1:0 VDI_MODE[1:0] R/W 4:3 VDI_MODE[4:3] R/W 2 VDI_MODE[2] is unused - 1:0 VDI_MODE[1:0] R/W 12NC 9397 750 ...
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Philips Semiconductors Volume Table 8: Global Registers …Continued Acces Bit Symbol s Offset 0x06 3004 VDO_MODE 31:8 Unused - 7 VDO_MODE R/W 12NC 9397 750 14321 Product data sheet Chapter 3: System On Chip Resources Value Description ...
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Philips Semiconductors Volume Table 8: Global Registers …Continued Acces Bit Symbol s 6 VDO_MODE R/W 5 VDO_MODE R/W 4:3 Unused - 12NC 9397 750 14321 Product data sheet Chapter 3: System On Chip Resources Value Description 0 ...
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Philips Semiconductors Volume Table 8: Global Registers …Continued Acces Bit Symbol s 2:0 VDO_MODE R/W 12NC 9397 750 14321 Product data sheet Chapter 3: System On Chip Resources Value Description 0 TFT/QVCP mapping to VDO interface 000*: ...
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Philips Semiconductors Volume Table 8: Global Registers …Continued Acces Bit Symbol s 12NC 9397 750 14321 Product data sheet Chapter 3: System On Chip Resources Value Description 100*: Digital 24-bit YUV or RGB video QVCP_DATA[29:22,19:12,9:2] -> VDO_D[28:5] ...
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Philips Semiconductors Volume Table 8: Global Registers …Continued Acces Bit Symbol s 2:0 VDO_MODE R/W [8-1] 12NC 9397 750 14321 Product data sheet Value Description 0 FGPO mapping to VDO interface 000* and VDO_MODE[7] = ‘1’: FGPO_DATA[2:0] ...
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Philips Semiconductors Volume Miscellaneous Several other system MMIO registers are described in the following paragraphs and detailed in the next • By default PCI_INTA_N is an input/output pin used in open drain mode for the PCI ...
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Philips Semiconductors Volume 8.1 Miscellaneous System MMIO registers Table 9: Miscellaneous System MMIO registers Acces Bit Symbol s System Registers Offset 0x06 3050 PCI_INTA 31:2 Unused - 1 PCI_INTA W 0 PCI_INTA_OE R/W Offset 0x06 3500 SCRATCH0 ...
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Philips Semiconductors Volume Table 9: Miscellaneous System MMIO registers Acces Bit Symbol s Offset 0x06 3600 SPDI_MUX_SEL 31:4 Unused - 3:0 SPDI_MUX_SEL R/W Offset 0x06 360C SPARE_CTRL 31:8 Unused - 7:0 SPARE_CTRL R/W 12NC 9397 750 14321 ...
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Philips Semiconductors Volume System Registers Map Summary Table 10: System Registers Map Summary Offset Name 0x06_3000 VDI _MODE 0x06_3004 VDO_MODE 0x06_3014 SYS_ENDIANESS 0x06_3050 PCI_INTA 0x06_3200 DCS_DRAM_LO 0x06_3204 DCS_DRAM_HI 0x06_3208 APERTURE_WE 0x06_3500 SCRATCH0 0x06_3504 SCRATCH1 0x06_3508 SCRATCH2 ...
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Philips Semiconductors Volume Table 10: System Registers Map Summary Offset Name 0x06_383C SEMAPHORE15 0x06_3FF4 GLB_REG_PWR_DWN 0x06_3FFC GLB_REG_MOD _ID 10. Simplified Internal Bus Infrastructure Figure 3: Simplified Internal Bus Infrastructure More details on the DCS bus in 12NC ...
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Philips Semiconductors Volume 11. MMIO Memory MAP Each module has an address range in the MMIO aperture from which its registers can be accessed. This address range is defined by its starting address, a.k.a. its offset, and ...
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Philips Semiconductors Volume Table 11: MMIO Memory MAP address offset from MMIO_BASE Module Module (PCI base 14) Name ID 0x10,4000 GPIO 0xA065 0x10,6000 VIP 0x011A 0x10,9000 SPDIF OUT 0x0121 0x10,A000 SPDIF IN 0x0110 0x10,C000 MBS 0x0119 0x10,E000 ...
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Chapter 4: Reset PNX15xx Series Data Book – Volume Rev. 2 — 1 December 2004 1. Introduction The Reset module initiates life for the PNX15xx Series system since it generates all reset signals required for a correct ...
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Philips Semiconductors Volume • peri_rst_n. This signal is used internally to reset all the PNX15xx Series modules including the TM3260 CPU. This signal is asserted when one of the following conditions occurs: – – – – Remark: ...
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Philips Semiconductors Volume Figure 1 PNX15xx Series system. Reset module Registers RST_CTL RST_CAUSE RESET_IN_N Watch Dog Timer POR_IN_N Interrupt Counter Bus Interface Figure 1: Reset Module Block Diagram 2.1 RESET_IN_N or POR_IN_N? POR_IN_N is meant to be ...
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Philips Semiconductors Volume 2.2 The watchdog Timer The internal PNX15xx Series watchdog timer has two operating modes. Both modes result in the assertion of the internal reset signals, peri_rst_n and sys_rst_out_n signals based upon a time-out condition. ...
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Philips Semiconductors Volume The following 1 clk_dtl_mmio Watchdog_count 0 watchdog_reset peri_rst_n sys_rst_out_n SYS_RST_OUT_N 1: The watchdog count register is programmed 2: The count is happening 3: The count reaches the programmed value and a watchdog reset is ...
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Philips Semiconductors Volume step 4 does not occur before the count reaches the WATCHDOG_COUNT value an interrupt is issued to the TM3260 CPU and the second internal counter (the interrupt counter) starts. The internal watchdog ...
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Philips Semiconductors Volume Remark: Upon any of the described ways to reset the PNX15xx Series system the ...
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Philips Semiconductors Volume 3.2 The Software Timing Whenever a watchdog timer time-out occurs or when a software reset is requested by writing to the RST_CTL.DO_SW_RST bit the PNX15xx Series system is reset. Both are referred as software ...
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Philips Semiconductors Volume Register Definitions Table 1: RESET Module Acces Bit Symbol s Reset Module Offset 0x06,0000 RST_CTL 31:3 Unused W 2 DO_SW_RST W 1 REL_SYS_RST_OUT W 0 ASSERT_SYS_RST_O W UT Offset 0x06,0004 RST_CAUSE Remark: RST_CTL ...
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Philips Semiconductors Volume Table 1: RESET Module …Continued Acces Bit Symbol s 0 WATCHDOG_INTERRU R/W PT_CLEAR Offset 0x06,0FEC INTERRUPT_SET 31:1 Unused R/W 0 WATCHDOG_INTERRU R/W PT_SET Offset 0x06,0FFC MODULE_ID 31:16 MODULE_ID R 15:12 MAJOR_REV R 11:8 MINOR_REV ...
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Chapter 5: The Clock Module PNX15xx Series Data Book – Volume Rev. 2 — 1 December 2004 1. Introduction The Clock module is the heart of the PNX15xx Series system. Its role is to provide and control ...
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Philips Semiconductors Volume • programmable dividers, controlled by configuration registers • clock blocking circuitry to allow for safe, glitch-free switching of clocks. Clocks are typically switched when: – – – – 12NC 9397 750 14321 Product data ...
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Philips Semiconductors Volume Figure 1 (DFT) have been added into the drawing and can be disregarded for functional behavior. The signals in functional operating mode. oscillator pad XTALI en xtal_clk low jitter PLL (external to CAB) XTALO ...
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Philips Semiconductors Volume Remark: Not all the clocks to the modules are generated in the Clock Module, there will be other clocks which will come into PNX15xx Series from external sources. Some of these clocks will be ...
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Philips Semiconductors Volume Table 1: PNX15xx Series Module and Bus Clocks Bus or Module Signal Name Description MBS clk_mbs MBS clock TMDBG clk_tstamp Timestamp clock GPIO 10/100 clk_lan Ethernet PHY Ethernet Clock MAC clk_lan_tx Ethernet Transmit Clock ...
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Philips Semiconductors Volume Table 1: PNX15xx Series Module and Bus Clocks Bus or Module Signal Name Description QVCP clk_qvcp_out VDO_CLK1 External pixel clock clk_qvcp_pix internal pixel clock clk_qvcp_proc processing layer clock clk_lcd_tstamp LCD timestamp VIP clk_vip VDI_CLK1 ...
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Philips Semiconductors Volume Table 1: PNX15xx Series Module and Bus Clocks Bus or Module Signal Name Description GPIO clk_gpio_4q GPIO FIFO clock clk_gpio_5q GPIO FIFO clock clk_gpio_6q_12 GPIO FIFO clock/ external clock clk_gpio_13 external clock clk_gpio_14 external ...
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Philips Semiconductors Volume 2.2.1 PLL Specification A PLL consists of a Voltage Controlled Oscillator (VCO) and a Post Divide (PD) circuit, as presented in Fpd Fin clk_in /M (xtal_clk) 5 extracted for DFT Figure 2: PLL Block ...
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Philips Semiconductors Volume • Run the VCO as high as possible, therefore for low output frequencies chose high P values • Ensure Table 2: Current Adjustment Values Based on N 30-37 38-46 47-54 55-63 64-72 73-82 83-89 ...
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Philips Semiconductors Volume PLL Characteristics Table 4: PLL Characteristics PLL Data Input clock frequency VCO input frequency VCO output frequency Output frequency Jitter (high frequency) Lock time Duty Cycle 2.2.2 The Clock Dividers The clock dividers allow ...
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Philips Semiconductors Volume 2.2.3 The DDS Clocks The DDS clocks are recommended for clocks that need to track dynamically another frequency by very small steps. The following equations characterize the PNX15xx Series DDS blocks DDS ...
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Philips Semiconductors Volume Table 7: External Clocks Signal Name Frequency mm_clk_out 200 MHz clk_mem clk_vip MHz clk_fgpi up to 100 MHz clk_qvcp MHz clk_fgpo up to 100 MHz ai_osclk ...
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Philips Semiconductors Volume 2.3 Clock Control Logic All the generated PNX15xx Series clocks follow the generic block diagram presented in Figure CAB clk_out BLOCKING Logic re-program PLL parameters or 1.728 GHz PLL divider Figure 3: Block Diagram ...
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Philips Semiconductors Volume The blocking will be released after a safe interval of 300 s. The 300 s is counted using the 27 MHz xtal_clk. blocking lasts for less than 10 xtal_clk cycles since it assumes the ...
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Philips Semiconductors Volume Table 8: Bypass Clock Sources Clocks from Clock Module clk_qvcp clk_qvcp_pix clk_qvcp_proc clk_lcd_tstamp clk_vip clk_vld ai_osclk ao_osclk clk_spdo clk_spdi clk_gpio_q4 clk_gpio_q5 clk_gpio_q6_12 clk_gpio_13 clk_gpio_14 clk_fgpo clk_fgpi 2.5 Power-up and Reset sequence On power-up, the ...
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Philips Semiconductors Volume write with a 0 value stops the clock stretching circuit. clk_tm stretcher count 3 0 turn_off turn_off_ack clk_out Figure 5: Clock Stretcher 2.7 Clock Frequency Determination This feature allows the measuring of the ...
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Philips Semiconductors Volume 2.8 Power Down All clocks generated in the clock module may be disabled by programming the relevant clock enable bit of each clock control register possible to gate module clocks in individual ...
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Philips Semiconductors Volume The GPIO interrupt comes from the GPIO block and is the “OR” of all the FIFO and timestamp registers. This way a GPIO pin can be monitored and when an event occurs the interrupt ...
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Philips Semiconductors Volume interrupt is generated whenever the signal 'clock present' changes status. Therefore an interrupt is generated if a clock changes from 'present' to 'non-present’ OR from 'non-present to 'present'. The interrupt registers are implemented ...
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Philips Semiconductors Volume protecting an input clock from contention by having the pad set to an input (in the case of an input clock). In both cases a write to each control register is necessary to properly ...
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Philips Semiconductors Volume 2.12.1 TM3260, DDR and QVCP clocks Clock xtal_clk PLL2 is located outside CAB PLL2 N,M, current_adj parameters slice_tst_in CAB PLL1 DDS1 PLL1 slice_tst_in 27 MHz N,M,P parameters Duty cycle 75/25 CAB PLL0 DDS0 slice_tst_in ...
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Philips Semiconductors Volume clk_144 clk_133 clk_108 clk_96 clk_86 clk_78 clk_58 clk_39 clk_33 clk_17 sel_qvcp_proc_clk_src Figure 8: QVCP_PROC Clock clk_qvcp_out Figure 9: QVCP_PIX Clock clk_qvcp_out generation is presented in clock used for clk_qvcp_out can be the inverted version ...
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Philips Semiconductors Volume 2.12.2 Clock Dividers 1.728 GHz PLL CAB Figure 10: Clock Dividers 12NC 9397 750 14321 Product data sheet Clocks Block clk_192 / clk_173 / clk_157 / clk_144 / clk_133 / clk_123 / clk_115 / ...
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Philips Semiconductors Volume 2.12.3 Internal PNX15xx Series Clock from Dividers clk_144 clk_123 clk_108 clk_96 clk_86 clk_78 clk_157 clk_72 clk_144 clk_54 clk_133 clk_123 clk_115 clk_108 clk_144 clk_102 clk_133 clk_54 clk_108 clk_96 clk_86 clk_78 clk_72 clk_66 sel_dtl_mmio_clk_src sel_vld_clk_src sel_dvdd_clk_src ...
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Philips Semiconductors Volume clk_33 xtal_clk/16 clk_144 clk_72 UNDEF clk_108 clk_13_5 clk_48 Figure 12: Internal PNX15xx Series Clock from Dividers: PCI, SPDI, LCD and I GPIO Figure 13: Internal PNX15xx Series Clock from Dividers: LCD Timestamp 12NC 9397 ...
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Philips Semiconductors Volume 2.12.4 GPIO Clocks Clock Module DDS8 tst_clk_a Clock Module DDS7 tst_clk_a Clock Module DDS6 tst_clk_a Clock Module DDS5 tst_clk_a Clock Module DDS2 tst_clk_a Figure 14: GPIO Clocks 12NC 9397 750 14321 Product data sheet ...
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Philips Semiconductors Volume 2.12.5 External Clocks xtal_clk DDS7 GPIO sel_clk_vip clk_vip Figure 15: VDI_CLK1 Block Diagram sel_clk_fgpi_src DDS3 DDS8 GPIO sel_clk_fgpi clk_fgpi Figure 16: VDI_CLK2 Block Diagram 12NC 9397 750 14321 Product data sheet Clock Module vip_output_enable_n ...
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Philips Semiconductors Volume xtal_clk PLL1 GPIO sel_clk_qvcp clk_lcd clk_qvcp_out qvcp_output_enable_n qvcp_output_select invert_clk_qvcp Figure 17: VDO_CLK1 Block Diagram xtal_clk PLL1 UNDEF DDS2 GPIO sel_clk_fgpo_src sel_clk_fgpo clk_fgpo Figure 18: VDO_CLK2 Block Diagram 12NC 9397 750 14321 Product data sheet ...
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Philips Semiconductors Volume Audio Output Module tps_ao_sck_oen tps_ao_sckout clk_ao_sck_o slice_tst_out DDS3 Figure 19: AO Clocks Audio Input Module tps_ai_sck_oen tps_ai_sckout clk_ai_sck_o slice_tst_out DDS4 Figure 20: AI Clocks 12NC 9397 750 14321 Product data sheet Clock Module BLOCKING ...
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Philips Semiconductors Volume UNDEF PLL1 DDS4 DDS7 sel_clk_lan_clk_src slice_tst_clk Figure 21: PHY LAN Clock Block Diagram CLK_LAN_R/TX Figure 22: Receive and Transmit LAN Clocks 12NC 9397 750 14321 Product data sheet tst_clk_lan xtal_clk BLOCKING GPIO sel_clk_lan tst_clk_lan ...
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Philips Semiconductors Volume 2.12.6 SPDO DDS5 Figure 23: SPDO Clock 3. Registers Definition 3.1 Registers Summary Table 10: Registers Summar Offset Name 0x04,7000 PLL0_CTL 0x04,7004 PLL1_CTL 0x04,7008 PLL2_CTL 0x04,700C PLL1_7_CTL 0x04,7010 DDS0_CTL 0x04,7014 DDS1_CTL 0x04,718 DDS2_CTL 0x04,701C ...
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Philips Semiconductors Volume Table 10: Registers Summar Offset Name 0x04,7124 CLK_IIC_CTL 0x04,7128 CLK_DVDD_CTL 0x04,712C CLK_MMIO_CTL 0x04,7130- RESERVED 0x04,71FC 0x04,7200 CLK_QVCP_OUT_CTL 0x04,7204 CLK_QVCP_PIX_CTL 0x04,7208 CLK_QVCP_PROC_CTL 0x04,720C CLK_LCD_TSTAMP_CTL 0x04,7210 CLK_VIP_CTL 0x04,7214 CLK_VLD_CTL 0x04,7218- RESERVED 0x04,72FC 0x04,7300 AI_OSCLK_CTL 0x04,7304 AI_SCK_CTL ...
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Philips Semiconductors Volume Table 10: Registers Summar Offset Name 0x04,7FEC INTERRUPT_SET 0x04,7FF0- RESERVED 0x04,7FF8 0x04,7FFC MODULE_ID 12NC 9397 750 14321 Product data sheet Description Set Clock Detection interrupts RESERVED Module Identification and revision information © Koninklijke Philips ...
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Philips Semiconductors Volume 3.2 Registers Description Table 11: CLOCK MODULE REGISTERS Acces Bit Symbol s PLL Registers Offset 0x04,7000 PLL0_CTL Reset values set for expected frequencies for faster boot-up, shorter boot code. 31:30 Reserved R/W 29 Turn ...
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Philips Semiconductors Volume Table 11: CLOCK MODULE REGISTERS Acces Bit Symbol s Offset 0x04,7008 PLL2_CTL Reset values set for expected frequencies for faster boot-up, shorter boot code. 31:30 Reserved R/W 29 Turn Off Acknowledge R 28 PLL ...
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Philips Semiconductors Volume Table 11: CLOCK MODULE REGISTERS Acces Bit Symbol s Offset 0x04,701C DDS3_CTL 31 Enable R/W 30:0 dds3_ctl[30:0] R/W Offset 0x04,7020 DD4_CTL 31 Enable R/W 30:0 dds4_ctl[30:0] R/W Offset 0x04,7024 DDS5_CTL 31 Enable R/W 30:0 ...
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Philips Semiconductors Volume Table 11: CLOCK MODULE REGISTERS Acces Bit Symbol s 1 pd_108 R/W 0 pd_102 R/W Offset 0x04,7038-0x04,70FCReserved Module Clocks Offset 0x04,7100 CLK_TM_CTL 31:6 Reserved R/W 5 turn_off_ack R 4 tm_stretch_n R/W 3 sel_pwrdwn_clk_mmio W ...
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Philips Semiconductors Volume Table 11: CLOCK MODULE REGISTERS Acces Bit Symbol s 3 turn_off_ack R 2:1 sel_clk_mem R/W 0 en_clk_mem R/W Offset 0x04,7108 CLK_2DDE_CTL 31:7 Reserved R/W 6 turn_off_ack R 5:3 sel_clk_2dde_src R/W 2:1 sel_clk_2dde R/W 0 ...
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Philips Semiconductors Volume Table 11: CLOCK MODULE REGISTERS Acces Bit Symbol s 6 turn_off_ack R 5:3 sel_clk_mbs_src R/W 2:1 sel_clk_mbs R/W 0 en_clk_mbs R/W Offset 0x04,7114 CLK_TSTAMP_CTL 31:4 Reserved R/W 3 turn_off_ack R 2:1 sel_clk_tstamp R/W 0 ...
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Philips Semiconductors Volume Table 11: CLOCK MODULE REGISTERS Acces Bit Symbol s 2:1 sel_clk_lan R/W 0 en_clk_lan R/W Offset 0x04,711C CLK_LAN_RX_CTL 31:4 Reserved R/W 3 turn_off_ack R 2:1 sel_clk_lan_rx R/W 0 en_clk_lan_rx R/W Offset 0x04,7120 CLK_LAN_TX_CTL 31:4 ...
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Philips Semiconductors Volume Table 11: CLOCK MODULE REGISTERS Acces Bit Symbol s 6 turn_off_ack R 5:3 sel_clk_dvdd_src R/W 2:1 sel_clk_dvdd R/W 0 en_clk_dvdd R/W Offset 0x04,712C CLK_DTL_MMIO_CTL 31:7 Reserved R/W 6 turn_off_ack R 5:3 sel_clk_dtl_mmio_src R/W 2:1 ...
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Philips Semiconductors Volume Table 11: CLOCK MODULE REGISTERS Acces Bit Symbol s 5 Invert_qvcp_clock R/W 4 qvcp_output_select R/W 3 qvcp_output_enable_n R/W 2:1 sel_clk_qvcp R/W 0 en_clk_qvcp R/W Offset 0x04,7204 CLK_QVCP_PIX_CTL 31:7 Reserved R/W 6 turn_off_ack R 5:3 ...
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Philips Semiconductors Volume Table 11: CLOCK MODULE REGISTERS Acces Bit Symbol s 0 en_clk_qvcp_pix R/W Offset 0x04,7208 CLK_QVCP_PROC_CTL 31:8 Reserved R/W 7 turn_off_ack R 6:3 sel_clk_qvcp_proc_src R/W 2:1 sel_clk_dtl_mmio R/W 0 en_clk_proc R/W Offset 0x04,720C CLK_LCD_TIMESTAMP_CTL 31:4 ...
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Philips Semiconductors Volume Table 11: CLOCK MODULE REGISTERS Acces Bit Symbol s 3 vip_output_enable_n R/W 2:1 sel_clk_vip R/W 0 en_clk_vip R/W Offset 0x04,7214 CLK_VLD_CTL 31:7 Reserved R/W 6 turn_off_ack R 5:3 sel_clk_vld_src R/W 2:1 sel_clk_vld R/W 0 ...
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Philips Semiconductors Volume Table 11: CLOCK MODULE REGISTERS Acces Bit Symbol s 31:3 Reserved R/W 2 turn_off_ack R 1 sel_clk_ai_sck R/W 0 en_clk_ai_sck R/W Offset 0x04,7308 CLK_AO_OSCLK 31:4 Reserved R/W 3 turn_off_ack R 2:1 sel_ao_osclk R/W 0 ...
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Philips Semiconductors Volume Table 11: CLOCK MODULE REGISTERS Acces Bit Symbol s 4 turn_off_ack R 3 sel_spdi_clk_src R/W 2:1 sel_spdi_clk R/W 0 en_clk_spdi R/W Offset 0x04,7318-0x04,73FCReserved General Purpose Offset 0x04,7400 CLK_GPIO_Q4_CTL 31:4 Reserved R/W 3 turn_off_ack R ...
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Philips Semiconductors Volume Table 11: CLOCK MODULE REGISTERS Acces Bit Symbol s 2:1 sel_clk_gpio_q6_12_ctl R/W 0 en_clk_gpio_q6_12_ctl R/W Offset 0x04,740C CLK_GPIO_13_CTL 31:4 Reserved R/W 3 turn_off_ack R 2:1 sel_clk_gpio_13_ctl R/W 0 en_clk_gpio_13_ctl R/W Offset 0x04,7410 CLK_GPIO_14_CTL 31:4 ...
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Philips Semiconductors Volume Table 11: CLOCK MODULE REGISTERS Acces Bit Symbol s 5 fgpo_output_enable_n R/W 4:3 sel_clk_fgpo_src R/W 2:1 sel_clk_fgpo R/W 0 en_clk_fgpo R/W Offset 0x04,7418 CLK_FGPI_CTL 31:6 Reserved R/W 5 turn_off_ack R 4 fgpi_output_enable_n R/W 3 ...
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Philips Semiconductors Volume Table 11: CLOCK MODULE REGISTERS Acces Bit Symbol s 31:0 count_stretcher_bits R/W Offset 0x04,7504 CLK_WAKEUP_CTL 31:2 count_wakeup_bits R/W 1 external_wakeup_enabl R gpio_interrupt_enable R/W Offset 0x04,7508 CLK_FREQ_CTL 31:5 freq_ctr_bits R/W 4 freq_ctr_done 3:0 ...
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Philips Semiconductors Volume Table 11: CLOCK MODULE REGISTERS Acces Bit Symbol s 9:8 Aligner_adjust_area2 R/W1 7:6 Aligner_adjust_area1 R/W1 5:4 Aligner_adjust_l_area0 R/W1 3:2 Aligner_adjust_e_area0 R/W1 1:0 Aligner_adjust R/W1 Offset 0x04,7514-FDC RESERVED Interrupt Registers Offset 0x04,7FE0 INTERRUPT STATUS 31 ...
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Philips Semiconductors Volume Table 11: CLOCK MODULE REGISTERS Acces Bit Symbol s 0 VDI_CLK1 (clk_vip) R/W Offset 0x04,7FE8 INTERRUPT CLEAR 31:5 Reserved W 4 VDO_CLK2 (clk_fgpo VDI_CLK2 (clk_fgpi AO_SCK W 1 AI_SCK W ...
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Philips Semiconductors Volume 12NC 9397 750 14321 Product data sheet © Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved. Rev. 2 — 1 December 2004 PNX15xx Series Chapter 5: The Clock Module 5-52 ...
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Chapter 6: Boot Module PNX15xx Series Data Book – Volume Rev. 2 — 1 December 2004 1. Introduction Before a PNX15xx Series system can begin operating, there are a couple of system related MMIO registers, PNX15xx Series ...
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Philips Semiconductors Volume 2.1 The Boot Modes The boot modes are defined by the state of the BOOT_MODE[7:0] pins at reset time. Therefore adequate pull-ups and pull-downs should be placed on the system board in order to ...
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Philips Semiconductors Volume Table 1: The Boot Modes …Continued BOOT_MODE GPIO Bits pins Default Function 3 3 0x0 2 2 0x1 1:0 1:0 0x3 The default state of the BOOT_MODE[3:0] pins may be determined by the internal ...
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Philips Semiconductors Volume 2.2 Boot Module Operation The following presents a high level block diagram of the boot module. DCS Bus Boot Module MMIO to DCS Bus Interface 27 MHz (clk_27) Figure 1: Boot Block Diagram The ...