PNX1501E,557 NXP Semiconductors, PNX1501E,557 Datasheet - Page 283

• Manufacturer Part Number: PNX1501E,557
• Description: IC MEDIA PROC 266MHZ 456-BGA
• Manufacturer: NXP Semiconductors

Specifications of PNX1501E,557

• Applications: Multimedia
• Core Processor: TriMedia
• Controller Series: Nexperia
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 61
• Voltage - Supply: 1.14 V ~ 1.26 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 456-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Type: -
• Ram Size: -
• Other names: 935274728557; PNX1501E; PNX1501E

Philips Semiconductors
Volume 1 of 1
PNX15XX_SER_3
Product data sheet
Several FIFOs Enabled
There is one DMA read channel and one DMA write channel available for the 4 FIFO
queues. Each FIFO queue only makes 64 byte DMA requests to one of the channels.
The bandwidth allocated by the central arbiter is done separately for the read channel
and for the write channel. The 4 FIFOs compete to access to the same DMA channel.
The arbitration between the 4 FIFOs is a priority encoded scheme. Every time there
is a slot available in the DMA channel the local arbiter looks for the request coming
from the 4 FIFOs in the order 0, 1, 2, and 3. There is up to 3 slots available in the
DMA channel. Each FIFO does ping-pong requests, i.e. a FIFO cannot have two
pending requests.
If the total system bandwidth available for the 4 FIFO queues in DMA read or DMA
write is 64 bytes per 40 s and if all FIFOs are in read mode or write mode then each
FIFO gets one 64-byte request per 4 times 40 s. If 2 FIFOs are in read mode and
the other two in write mode and, at system level, the read DMA channel can get one
64-byte request per 40 s and the write DMA channel can also get one 64-byte
request per 40 s, then each FIFO can get one 64-byte request per 2x40 s.
So, in this situation the monitored/generated signal frequencies that can be tolerated
are:
Remark: The following sampling calculations assume 1-bit sampling (EN_IO_SEL =
00 or 11).
Timestamping: 1 edge -> 32 bits
=> 16 edges = 64 bytes of data
=> 16 edges can occur every 2x40 s
=> 1 edge can occur every 5 s = 200 kHz maximum frequency.
Sampling: 1 edge -> 1 bit
=> 512 edges = 64 bytes of data
=> 512 edges can occur every 2x40 s
=> 1 edge can occur every 156.25 ns = 6.4 MHz maximum frequency.
Similar calculations for frequency tolerances can be made for 2 or 3 queues
requesting DMA in the same direction and at the same time and for queues which
use multi-bit sampling, i.e. EN_IO_SEL set to binary code 01 or 10.
Remark: The computation can be made to answer a different question: if the signal
to sample is running at 12 MHz, then a sampling frequency of more than 24 MHz is
required then what is the minimum latency requirement for my system memory?
Similarly, if several FIFOs are operating simultaneously with different operating
frequencies (to sample different types of signals) then the different FIFOs will get
different maximum operating frequencies because of the local arbitration.
Rev. 3 — 17 March 2006
Chapter 8: General Purpose Input Output Pins
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX15xx Series
8-16