PNX1501E,557 NXP Semiconductors, PNX1501E,557 Datasheet - Page 285

• Manufacturer Part Number: PNX1501E,557
• Description: IC MEDIA PROC 266MHZ 456-BGA
• Manufacturer: NXP Semiconductors

Specifications of PNX1501E,557

• Applications: Multimedia
• Core Processor: TriMedia
• Controller Series: Nexperia
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 61
• Voltage - Supply: 1.14 V ~ 1.26 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 456-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Type: -
• Ram Size: -
• Other names: 935274728557; PNX1501E; PNX1501E

Philips Semiconductors
Volume 1 of 1
3. IR Applications
Table 5: Example of IR Characteristics
PNX15XX_SER_3
Product data sheet
PROTOCOL
CIR (IrDA Control)
CIR with Sub-Carrier (TX)
RC-MM
RC-MM Sub-Carrier
a
RF sub-carrier is 36kHz, ONTIME should be between 25-50% of 27.77us period. (108KHz = 33%)
2.7 Timer Sources
2.8 Wake-up Interrupt
2.9 External Watchdog
MIN. PULSE
6.67 s
0.667 s
27.77 s
9.26 s
The 12 timestamp unit interrupts are ORed together (if enabled) to produce one
interrupt. Therefore the 12 TSUs produce only one interrupt, see
page 3-12
All the interrupt status bits are ‘sticky’ bits and can only be cleared by writing a ‘1’ to
the relevant interrupt clear register. The GPIO status MMIO register,
VIC_INT_STATUS
TSU caused the interrupt.
Any of the GPIO pins or internal signals can be selected as a timer source for
TM3260, see
TIMER_IO_SEL MMIO register, see
An interrupt called ‘gpio_interrupt’ is generated whenever the GPIO module requests
an interrupt. This event is a ‘wake-up’ interrupt for the clock module to turn back on
the system clocks once the PNX15xx Series has been sent into deep sleep mode.
Any of the GPIO pin can be used in case of an external watchdog style reset
generator as the output which is pulsed regularly by software to keep a reset from
occurring. WDOG_OUT pin is a regular GPIO pin without any special properties, and
can be used as an extra GPIO if no watchdog reset is present.
For each FIFO queue programmed in signal monitoring or pattern generation modes,
it is possible to divide the 108 MHz clock to obtain suitable frequencies for Ir
applications.
As well as the 16-bit divider to divide the 108 MHz clock, each FIFO queue has a
further 5-bit divider which can be enabled if sub-carrier frequencies are required for
transmission. Therefore, in Ir applications, a FIFO queue can produce Ir signals at a
a
for SOURCE number allocation.
Table 6 on page
REQ. FREQ
150 kHz
1.5 MHz
36 kHz
108 kHz
Rev. 3 — 17 March 2006
Section
4.9, stores information about whether a FIFO queue or a
FREQ_DIV[15:0]
0x2D0
0x24
0xBB8
0x1F4
3-14. The selection is done by programming the
Chapter 8: General Purpose Input Output Pins
Section
4.8.
CARRIER_DIV[4:0]
0x1 or Disabled
0x14
0x1 or Disabled
0x6
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX15xx Series
Table 5 on
Error (%)
0
0
0
0
8-18