PNX1501E,557 NXP Semiconductors, PNX1501E,557 Datasheet - Page 318

• Manufacturer Part Number: PNX1501E,557
• Description: IC MEDIA PROC 266MHZ 456-BGA
• Manufacturer: NXP Semiconductors

Specifications of PNX1501E,557

• Applications: Multimedia
• Core Processor: TriMedia
• Controller Series: Nexperia
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 61
• Voltage - Supply: 1.14 V ~ 1.26 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 456-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Type: -
• Ram Size: -
• Other names: 935274728557; PNX1501E; PNX1501E

Philips Semiconductors
Volume 1 of 1
PNX15XX_SER_3
Product data sheet
Figure 3:
CPU_LIMIT
CPU_CLIP
CPU account
CPU account
#cycles_in_burst
CPU_RATIO
transfers
If there is no DMA then the CPU can still get the BW which it has to pay for by
allowing the CPU account to borrow from its future budget. If there is a longer time
period where there is no DMA traffic, the CPU account could potentially build up a
huge debt. As soon as DMA traffic restarts, the CPU could conceivably have an
extended period of time where they have a lower priority than DMA (while paying off
the debt). The CPU_CLIP value controls how much debt the CPU account is allowed
to build up. After that value has been reached and there is still no DMA traffic the
CPU will get the bandwidth for free. The number of data transfer cycles is accounted
for to approximately (excluding overhead) get the same account value before and
after the free transaction.
In the time zone marked “constant average account below clip” in
transfer rate is such that the average value of the CPU account is constant. In this
zone, we have the following equilibrium:
Where #cycles_in_burst is the nominal number of cycles it takes to complete a DDR
burst, being half of the burst length, and #cycles_between_arbitration is the number
of clock cycles between 2 successive CPU transfers win arbitration.
From this the CPU bandwidth (as percentage of maximum achievable) with constant
average account is derived:
In the time zone marked “constant average account above clip” in
transfer rate is such that the average value of the CPU account is constant. In this
zone, we have the following equilibrium:
CPU_RATIO
CPU_BW
#cycles_in_burst
slope = CPU_DECR/cycle
=
-------------------------------------------------------------------- -
#cycles_between_arbitration
+
#cycles_in_burst
=
constant average account above clip
#cycles_in_burst
Rev. 3 — 17 March 2006
CPU_DECR #cycles_between_arbitration
=
constant average account below clip,
see text
see text,
CPU_DECR #cycles_between_arbitration
=
------------------------------------------------- -
1
+
--------------------------------------- -
#cycles_in_burst
CPU_DECR
CPU_RATIO
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Chapter 9: DDR Controller
PNX15xx Series
Figure
Figure
time
3, the
3, the
9-5