XC4VFX60-10FFG1152C Xilinx Inc, XC4VFX60-10FFG1152C Datasheet - Page 388

IC FPGA VIRTEX-4 FX 60K 1152FBGA

XC4VFX60-10FFG1152C

Manufacturer Part Number
XC4VFX60-10FFG1152C
Description
IC FPGA VIRTEX-4 FX 60K 1152FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r

Specifications of XC4VFX60-10FFG1152C

Total Ram Bits
4276224
Number Of Logic Elements/cells
56880
Number Of Labs/clbs
6320
Number Of I /o
576
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-BBGA, FCBGA
No. Of Logic Blocks
6656
No. Of Macrocells
56880
Family Type
Virtex-4
No. Of Speed Grades
10
No. Of I/o's
576
Clock Management
DCM
Core Supply
RoHS Compliant
Package
1152FCBGA
Family Name
Virtex®-4
Device Logic Units
56880
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
576
Ram Bits
4276224
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
HW-V4-ML410-UNI-G - EVALUATION PLATFORM VIRTEX-4
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XC4VFX60-10FFG1152C
Manufacturer:
XilinxInc
Quantity:
3 000
Part Number:
XC4VFX60-10FFG1152C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC4VFX60-10FFG1152C
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XILINX
0
Part Number:
XC4VFX60-10FFG1152C
0
Chapter 8: Advanced SelectIO Logic Resources
Table 8-7: OSERDES Port List and Definitions
388
OQ
SHIFTOUT1
SHIFTOUT2
TQ
CLK
CLKDIV
D1 – D6
Port Name
OSERDES Primitive
OSERDES Ports
Output
Output
Output
Output
Input
Input
Input
Type
The OSERDES primitive is shown in
Table 8-7
1 (each)
Width
1
1
1
1
1
1
SHIFTIN1
SHIFTIN2
CLK
CLKDIV
D1
D2
D3
D4
D5
D6
OCE
REV
SR
T1
T2
T3
T4
TCE
lists the available ports in the OSERDES primitive.
Data path output.
Carry out for data width expansion. Connect to SHIFTIN1 of master OSERDES.
See
Carry out for data width expansion. Connect to SHIFTIN2 of master OSERDES.
See
3-state control output.
High-speed clock input. Clocks serialized data to OQ output.
Divided clock input. Clocks parallel data at D1-D6 inputs into OSERDES.
Parallel data inputs.
“OSERDES Width
“OSERDES Width
www.xilinx.com
Figure 8-15: OSERDES Primitive
Expansion”.
Expansion”.
Figure
8-15.
Description
UG070 (v2.6) December 1, 2008
Virtex-4 FPGA User Guide
UG070_8_19_031208
SHIFTOUT1
SHIFTOUT2
TQ
OQ
R

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