XC4VFX60-10FFG1152C Xilinx Inc, XC4VFX60-10FFG1152C Datasheet - Page 263

• Manufacturer Part Number: XC4VFX60-10FFG1152C
• Description: IC FPGA VIRTEX-4 FX 60K 1152FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX60-10FFG1152C

• Total Ram Bits: 4276224
• Number Of Logic Elements/cells: 56880
• Number Of Labs/clbs: 6320
• Number Of I /o: 576
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-BBGA, FCBGA
• No. Of Logic Blocks: 6656
• No. Of Macrocells: 56880
• Family Type: Virtex-4
• No. Of Speed Grades: 10
• No. Of I/o's: 576
• Clock Management: DCM
• Core Supply: RoHS Compliant
• Package: 1152FCBGA
• Family Name: Virtex®-4
• Device Logic Units: 56880
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 576
• Ram Bits: 4276224
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V4-ML410-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
HSTL (High-Speed Transceiver Logic)
R
HSTL_ I, HSTL_ III, HSTL_ I_18, HSTL_ III_18 Usage
HSTL_ I_DCI, HSTL_ III_DCI, HSTL_ I_DCI_18, HSTL_ III_DCI_18 Usage
Table 6-12
Table 6-12: GTLP DC Voltage Specifications
Table 6-13
Table 6-13: Allowed Attributes of the GTLP I/O Standards
The High-Speed Transceiver Logic (HSTL) standard is a general-purpose high-speed, 1.5V
or 1.8V bus standard sponsored by IBM (EIA/JESD8-6). This standard has four variations
or classes. To support clocking high-speed memory interfaces, a CSE differential version of
this standard was added. Virtex-4 FPGA I/O supports all four classes and the differential
version. This standard requires a differential amplifier input buffer and a push-pull output
buffer.
HSTL_I uses V
parallel termination voltage (V
unidirectional links.
HSTL_I_DCI provides on-chip split thevenin termination powered from V
equivalent parallel termination voltage (V
are intended to be used in unidirectional links.
Notes:
1. N must be greater than or equal to 0.653 and less than or equal to 0.68.
V
V
V
V
V
V
V
I
I
I
IOSTANDARD
CAPACITANCE
OH
OL
OL
CCO
REF
TT
IH
IL
OH
OL
at V
at V
= V
at V
= V
= N × V
Attributes
REF
REF
OL
OL
OH
lists the GTLP DC voltage specifications.
details the allowed attributes that can be applied to the GTLP I/O standards.
(mA) at 0.6V
(mA) at 0.3V
– 0.1
+ 0.1
(mA)
TT
CCO
(1)
/2 as a parallel termination voltage (V
Specific Guidelines for Virtex-4 FPGA I/O Supported Standards
www.xilinx.com
TT
). HSTL_I and HSTL_III are intended to be used in
Input
TT
LOW, NORMAL, DONT_CARE
) of V
Min
0.88
1.35
0.98
GTLP and GTLP_DCI
0.3
36
–
–
–
–
–
CCO
/2. HSTL_I_DCI and HSTL_III_DCI
Output
TT
). HSTL_III uses V
Typ
0.45
1.0
1.5
1.1
0.9
–
–
–
–
–
Bidirectional
CCO
Max
1.12
1.65
1.02
0.6
48
–
–
–
–
–
, creating an
CCO
as a
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