XC4VFX60-10FFG1152C Xilinx Inc, XC4VFX60-10FFG1152C Datasheet - Page 253

IC FPGA VIRTEX-4 FX 60K 1152FBGA

XC4VFX60-10FFG1152C

Manufacturer Part Number
XC4VFX60-10FFG1152C
Description
IC FPGA VIRTEX-4 FX 60K 1152FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r

Specifications of XC4VFX60-10FFG1152C

Total Ram Bits
4276224
Number Of Logic Elements/cells
56880
Number Of Labs/clbs
6320
Number Of I /o
576
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-BBGA, FCBGA
No. Of Logic Blocks
6656
No. Of Macrocells
56880
Family Type
Virtex-4
No. Of Speed Grades
10
No. Of I/o's
576
Clock Management
DCM
Core Supply
RoHS Compliant
Package
1152FCBGA
Family Name
Virtex®-4
Device Logic Units
56880
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
576
Ram Bits
4276224
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
HW-V4-ML410-UNI-G - EVALUATION PLATFORM VIRTEX-4
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

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XC4VFX60-10FFG1152C
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Part Number:
XC4VFX60-10FFG1152C
Manufacturer:
Xilinx Inc
Quantity:
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Part Number:
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Specific Guidelines for Virtex-4 FPGA I/O Supported Standards
Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
LVTTL (Low Voltage Transistor-Transistor Logic)
R
The following sections provide an overview of the I/O standards supported by all Virtex-4
devices.
While most Virtex-4 FPGA I/O supported standards specify a range of allowed voltages,
this chapter records typical voltage values only. Detailed information on each specification
can be found on the Electronic Industry Alliance JEDEC website at
The low-voltage TTL (LVTTL) standard is a general purpose EIA/JESDSA standard for
3.3V applications using an LVTTL input buffer and a push-pull output buffer. This
standard requires a 3.3V input and output supply voltage (V
use of a reference voltage (V
Sample circuits illustrating both unidirectional and bidirectional LVTTL termination
techniques are shown in
LVTTL
LVTTL
LVTTL
Figure 6-25: LVTTL Unidirectional Termination
Specific Guidelines for Virtex-4 FPGA I/O Supported Standards
Figure 6-25
IOB
IOB
IOB
Note: V
www.xilinx.com
REF
TT
) or a termination voltage (V
R S = Z 0 – R D
is any voltage from 0V to V CCO
R P = Z 0
Z 0
and
Z 0
Figure
Z 0
V
TT
6-26.
IOB
IOB
IOB
LVTTL
LVTTL
LVTTL
CCO
TT
).
), but does not require the
ug070_6_25_071904
http://www.jedec.org.
253

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