XC4VFX60-10FFG1152C Xilinx Inc, XC4VFX60-10FFG1152C Datasheet - Page 339

• Manufacturer Part Number: XC4VFX60-10FFG1152C
• Description: IC FPGA VIRTEX-4 FX 60K 1152FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX60-10FFG1152C

• Total Ram Bits: 4276224
• Number Of Logic Elements/cells: 56880
• Number Of Labs/clbs: 6320
• Number Of I /o: 576
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-BBGA, FCBGA
• No. Of Logic Blocks: 6656
• No. Of Macrocells: 56880
• Family Type: Virtex-4
• No. Of Speed Grades: 10
• No. Of I/o's: 576
• Clock Management: DCM
• Core Supply: RoHS Compliant
• Package: 1152FCBGA
• Family Name: Virtex®-4
• Device Logic Units: 56880
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 576
• Ram Bits: 4276224
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V4-ML410-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
R
Verilog Code for Fixed Delay Mode
Variable Delay Mode
The following code shows how to instantiate the IDELAY module in variable delay mode.
IDELAYCTRL must also be instantiated when operating in this mode (see
Overview,” page
VHDL Code for Variable Delay Mode
// The IDELAYCTRL primitive must be instantiated in conjunction with
// IDELAY
// primitive when used in Fixed Delay Mode.
// Module: IDELAY
// Description: Verilog instantiation template
// Fixed Delay Mode
//
// Device: Virtex-4 Family
//-------------------------------------------------------------------
// Instantiation Section
//
IDELAY U1
//Set IOBDELAY_TYPE attribute to FIXED for Fixed Delay Mode
//synthesis attribute IOBDELAY_TYPE of U1 is "FIXED";
//Set IOBDELAY_VALUE attribute to 31 for center of delay element
//synthesis attribute IOBDELAY_VALUE of U1 is 31;
-- The IDELAYCTRL primitive must be instantiated in conjunction with the
IDELAY
-- primitive when used in Variable Delay Mode.
-- Module: IDELAY
-- Description: VHDL instantiation template
-- Variable Delay Mode
--
-- Device: Virtex-4 Family
---------------------------------------------------------------------
-- Components Declarations
-- Component Declaration for IDELAY should be placed
-- after architecture statement but before "begin" keyword
component IDELAY
generic (
(
);
O(data_output)
I(data_input),
C(1’b0),
CE(1’b0),
INC(1’b0),
RST(1’b0)
);
C => ’0’,
CE => ’0’,
INC => ’0’,
RST => ’0’
341).
www.xilinx.com
ILOGIC Resources
“IDELAYCTRL
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