XC4VFX60-10FFG1152C Xilinx Inc, XC4VFX60-10FFG1152C Datasheet - Page 164

• Manufacturer Part Number: XC4VFX60-10FFG1152C
• Description: IC FPGA VIRTEX-4 FX 60K 1152FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX60-10FFG1152C

• Total Ram Bits: 4276224
• Number Of Logic Elements/cells: 56880
• Number Of Labs/clbs: 6320
• Number Of I /o: 576
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-BBGA, FCBGA
• No. Of Logic Blocks: 6656
• No. Of Macrocells: 56880
• Family Type: Virtex-4
• No. Of Speed Grades: 10
• No. Of I/o's: 576
• Clock Management: DCM
• Core Supply: RoHS Compliant
• Package: 1152FCBGA
• Family Name: Virtex®-4
• Device Logic Units: 56880
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 576
• Ram Bits: 4276224
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V4-ML410-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 4: Block RAM
FIFO Applications
164
Cascading FIFOs to Increase Depth
Cascading FIFOs to Increase Width
There are various uses for the Virtex-4 FPGA block RAM FIFO:
•
•
Figure 4-22
FIFO in FWFT mode, and uses external resources to connect to the second FIFO. The
ALMOST_FULL_OFFSET of the second FIFO should be four or more. The data latency of
this application can be up to double that of a single FIFO, and the maximum frequency is
limited by the feedback path. The NOR gate is implemented using CLB logic.
As shown in
design. CLB logic is used to implement the AND/OR gates. The maximum frequency can
be limited by the logic gate feedback path.
DIN[71:36]
DIN[35:0]
DIN[3:0]
WRCLK
RDCLK
WRCLK
WREN
Cascading two asynchronous FIFOs to form a deeper FIFO
Building wider asynchronous FIFO by connecting two FIFOs in parallel.
RDEN
RDCLK
WREN
RDEN
shows a way of cascading FIFOs to increase depth. The application sets the first
512 x 72 FIFO
Figure
DIN[3:0]
WREN
RDEN
WRCLK
RDCLK
4-23, the Virtex-4 FPGA FIFO can be cascaded to add width to the
FIFO #1
Figure 4-23: Cascading FIFO by Width
www.xilinx.com
DOUT[3:0]
Figure 4-22: Cascading FIFO
EMPTY
DIN[35:0]
WREN
RDEN
WRCLK
RDCLK
DIN[35:0]
WREN
RDEN
WRCLK
RDCLK
FIFO #1
FIFO #2
DOUT[35:0]
DOUT[35:0]
DIN[3:0]
WREN
RDEN
WRCLK
RDCLK
EMPTY
EMPTY
AFULL
AFULL
FIFO #2
DOUT[3:0]
UG070 (v2.6) December 1, 2008
AFULL
8K x 4 FIFO
Virtex-4 FPGA User Guide
UG070_4_23_030708
UG070_4_24_030708
DOUT[3:0]
DOUT[35:0]
EMPTY
DOUT[71:36]
AFULL
R