XC4VFX60-10FFG1152C Xilinx Inc, XC4VFX60-10FFG1152C Datasheet - Page 366

• Manufacturer Part Number: XC4VFX60-10FFG1152C
• Description: IC FPGA VIRTEX-4 FX 60K 1152FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX60-10FFG1152C

• Total Ram Bits: 4276224
• Number Of Logic Elements/cells: 56880
• Number Of Labs/clbs: 6320
• Number Of I /o: 576
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-BBGA, FCBGA
• No. Of Logic Blocks: 6656
• No. Of Macrocells: 56880
• Family Type: Virtex-4
• No. Of Speed Grades: 10
• No. Of I/o's: 576
• Clock Management: DCM
• Core Supply: RoHS Compliant
• Package: 1152FCBGA
• Family Name: Virtex®-4
• Device Logic Units: 56880
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 576
• Ram Bits: 4276224
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V4-ML410-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 8: Advanced SelectIO Logic Resources
366
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•
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Figure 8-1
components and features of the block.
DLYRST
CLKDIV
DLYINC
DLYCE
OCLK
Bitslip
c.
The section
Bitslip Submodule
The Bitslip submodule allows designers to reorder the sequence of the parallel data
stream going into the FPGA logic. This can be used for training source-synchronous
interfaces that include a training pattern.
Dedicated Support for Strobe-based Memory Interfaces
ISERDES contains dedicated circuitry (including the OCLK input pin) to handle the
strobe-to-FPGA clock domain crossover entirely within the ISERDES block. This
allows for higher performance and a simplified implementation.
Dedicated support for Networking interfaces.
REV
CE1
CE2
CLK
SR
D
VARIABLE – Delay value can be changed at run-time by manipulating a set of
control signals
shows the block diagram of the ISERDES, highlighting all the major
“Input Delay Element (IDELAY)” in Chapter 7
IDELAY
Module
Figure 8-1: ISERDES Block Diagram
www.xilinx.com
CE
Serial to Parallel
Converter
BITSLIP
Module
UG070 (v2.6) December 1, 2008
discusses IDELAY in detail.
Virtex-4 FPGA User Guide
O
SHIFTIN1/2
SHIFTOUT1/2
Q1 - Q6
UG70_8_01_031208
R