XC4VFX60-10FFG1152C Xilinx Inc, XC4VFX60-10FFG1152C Datasheet - Page 126

• Manufacturer Part Number: XC4VFX60-10FFG1152C
• Description: IC FPGA VIRTEX-4 FX 60K 1152FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX60-10FFG1152C

• Total Ram Bits: 4276224
• Number Of Logic Elements/cells: 56880
• Number Of Labs/clbs: 6320
• Number Of I /o: 576
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-BBGA, FCBGA
• No. Of Logic Blocks: 6656
• No. Of Macrocells: 56880
• Family Type: Virtex-4
• No. Of Speed Grades: 10
• No. Of I/o's: 576
• Clock Management: DCM
• Core Supply: RoHS Compliant
• Package: 1152FCBGA
• Family Name: Virtex®-4
• Device Logic Units: 56880
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 576
• Ram Bits: 4276224
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V4-ML410-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 4: Block RAM
126
Data-Out Buses - DO[A|B]<#:0> and DOP[A|B]<#:0>
Cascade - CASCADEIN[A|B]
Cascade - CASCADEOUT[A|B]
Inverting Control Pins
GSR
Unused Inputs
width. For example the 36-bit port data width is represented by DI<31:0> and DIP<3:0>, as
shown in
Data-out buses reflect the contents of memory cells referenced by the address bus at the
last active clock edge during a read operation. During a write operation (WRITE_FIRST or
READ_FIRST configuration), the data-out buses reflect either the data-in buses or the
stored value before write. During a write operation in NO_CHANGE mode, data-out
buses are not affected. The regular data-out bus (DO) and the parity data-out bus (DOP)
(when available) have a total width equal to the port width, as shown in
The CASCADEIN pins are used to connect two block RAMs to form the 32K x 1 mode. This
pin is used when the block RAM is the UPPER block RAM, and is connected to the
CASCADEOUT pins of the LOWER block RAM. When cascade mode is not used, this pin
does not need to be connected. Refer to the
information.
The CASCADEOUT pins are used to connect two block RAMs to form the 32K x 1 mode.
This pin is used when the block RAM is the LOWER block RAM, and is connected to the
CASCADEIN pins of the UPPER block RAM. When cascade mode is not used, this pin
does not need to be connected. Refer to the
information.
For each port, the five control pins (CLK, EN, WE, REGCE, and SSR) each have an
individual inversion option. Any control signal can be configured as active High or Low,
and the clock can be active on a rising or falling edge (active High on rising edge by
default) without requiring other logic resources.
The global set/reset (GSR) signal of a Virtex-4 device is an asynchronous global signal that
is active at the end of device configuration. The GSR can also restore the initial Virtex-4
FPGA state at any time. The GSR signal initializes the output latches to the INIT, or to the
INIT_A and INIT_B value (see
internal memory contents. Because it is a global signal, the GSR has no input pin at the
functional level (block RAM primitive).
Unused Data and/or address inputs should be tied High.
Table
4-2.
www.xilinx.com
“Block RAM
“Cascadable Block RAM”
“Cascadable Block RAM”
Attributes”). A GSR signal has no impact on
UG070 (v2.6) December 1, 2008
Virtex-4 FPGA User Guide
for further
for further
Table
4-2.
R