XC4VFX60-10FFG1152C Xilinx Inc, XC4VFX60-10FFG1152C Datasheet - Page 109

• Manufacturer Part Number: XC4VFX60-10FFG1152C
• Description: IC FPGA VIRTEX-4 FX 60K 1152FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX60-10FFG1152C

• Total Ram Bits: 4276224
• Number Of Logic Elements/cells: 56880
• Number Of Labs/clbs: 6320
• Number Of I /o: 576
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-BBGA, FCBGA
• No. Of Logic Blocks: 6656
• No. Of Macrocells: 56880
• Family Type: Virtex-4
• No. Of Speed Grades: 10
• No. Of I/o's: 576
• Clock Management: DCM
• Core Supply: RoHS Compliant
• Package: 1152FCBGA
• Family Name: Virtex®-4
• Device Logic Units: 56880
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 576
• Ram Bits: 4276224
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V4-ML410-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

VHDL and Verilog Templates, and the Clocking Wizard
Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
R
Figure 3-12
series. Note the following guidelines:
•
The
Libraries Guide for all primitives. In addition, VHDL and Verilog files are generated by the
Clocking Wizard in the ISE® software. The Clocking Wizard sets appropriate DCM and
single/parallel PMCD configurations.
The Clocking Wizard is accessed using the ISE software, in the Project Navigator. Refer to
the Xilinx®
1.
2.
3.
4.
5.
6.
Figure 3-13
with the PMCD. To access further information on available settings, choose the More Info
button in each window.
GCLK
IOB
A dedicated local connection exists from the CLKA1D8 output of each PMCD to the
CLKA and CLKB inputs of the other PMCD within the same tile (group of two). Thus,
only CLKA1D8 can directly connect two PMCDs in series.
From the Project Navigator menu, select Project -> New Source. The New Source
window appears.
Enter a file name and select IP (CoreGen and Architecture Wizard).
Click Next. The Select Core Type window appears.
Select Clocking -> Single DCM_ADV, click next. The New Source Information window
appears.
Click Finish.
The Clocking Wizard starts.
“VHDL Template,” page 111
RST_DEASSERT_CLK = CLKA
EN_REL = FALSE
Reset
illustrates an example of dividing clock frequencies using two PMCDs in
and
Software Manuals
Figure 3-12: PMCD to PMCD for Clock Frequency Division
Figure 3-14
CLKA
RST
REL
PMCD
www.xilinx.com
show the settings in the Clocking Wizard for using the DCM
CLKA1D8
for more information on ISE software.
VHDL and Verilog Templates, and the Clocking Wizard
and
“Verilog Template,” page 112
Reset
f/8
RST_DEASSERT_CLK = CLKA
EN_REL = FALSE
CLKA
RST
REL
PMCD
CLKA1D8
are also available in the
UG070_3_12_071404
BUFG
f/64
109