XC4VFX60-10FFG1152C Xilinx Inc, XC4VFX60-10FFG1152C Datasheet - Page 315

• Manufacturer Part Number: XC4VFX60-10FFG1152C
• Description: IC FPGA VIRTEX-4 FX 60K 1152FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX60-10FFG1152C

• Total Ram Bits: 4276224
• Number Of Logic Elements/cells: 56880
• Number Of Labs/clbs: 6320
• Number Of I /o: 576
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-BBGA, FCBGA
• No. Of Logic Blocks: 6656
• No. Of Macrocells: 56880
• Family Type: Virtex-4
• No. Of Speed Grades: 10
• No. Of I/o's: 576
• Clock Management: DCM
• Core Supply: RoHS Compliant
• Package: 1152FCBGA
• Family Name: Virtex®-4
• Device Logic Units: 56880
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 576
• Ram Bits: 4276224
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V4-ML410-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
Parasitic Factors Derating Method (PFDM)
R
the voltage induced across power system parasitics by supply current transients. One
cause of current transients is output driver switching events. Numerous output switching
events occurring at the same time lead to bigger current transients, and therefore bigger
induced voltages (ground bounce, V
paths exist in the die, package, and PCB, therefore, parasitics from all three must be
considered. The larger the value of these parasitics, the larger the voltage induced by a
current transient (power-supply disturbance).
V
bounce also affects inputs configured as certain I/O standards because they interpret
incoming signals by comparing them to a threshold referenced to the die ground (as
opposed to I/O standards with input thresholds referenced to a V
voltage disturbance exceeds the instantaneous noise margin for the interface, then a non-
changing input or output can be interpreted as changing.
This section describes a method to evaluate whether a design is within the SSO limits when
taking into account the specific electrical characteristics of the user's unique system.
The SSO limits in
of the system. These factors fall into three groups of electrical characteristics:
•
•
•
When the electrical characteristics of a design differ from the nominal values, the system
SSO limit changes. The degree of difference determines the new effective limit for the
design. A figure called “SSO Allowance” is used as a single derating factor, taking into
account the combined effect of all three groups of system electrical characteristics.
The SSO allowance is a number ranging from 0 to 100% and is a product of three scaling
factors:
The First Scaling Factor accounts for the PCB PDS parasitic inductance. It is determined by
dividing the nominal PCB PDS inductance by the user's PCB PDS inductance, L
The PCB PDS inductance is determined based on a set of board geometries: board
thickness, via diameter, breakout trace width and length, and any other additional
structures including sockets.
The Second Scaling Factor accounts for the maximum allowable power system disturbance.
It is determined by dividing the user's maximum allowable power system disturbance,
(V
V
voltage and input logic low threshold.
The Third Scaling Factor accounts for the capacitive loading of outputs driven by the FPGA.
It is based on the transient current impact of every additional picofarad of load capacitance
above the assumed nominal. For every additional 1 pF of load capacitance over the
nominal, approximately 9 mV of additional power system disturbance will occur. The
additional power system disturbance is compared to the nominal power system
disturbance, and a scale factor is derived from the relationship. C
average load capacitance.
Example calculations show how each scale factor is computed, as well as the SSO
allowance. The system parameters used in this example are:
CC
DISTURBANCE_USER
DISTURBANCE_USER
PCB PDS parasitics (nominal 1 nH per via)
Maximum allowable power system disturbance voltage (nominal 600 mV)
Capacitive loading (nominal 10 pF per load)
bounce affects stable high outputs. Ground bounce affects stable low outputs. Ground
Table 6-40
is usually determined by taking the lesser of input undershoot
) by the nominal maximum power system disturbance.
www.xilinx.com
and
Table 6-42
CC
bounce, or rail collapse). Relevant transient current
assume nominal values for the parasitic factors
Simultaneous Switching Output Limits
LOAD_USER
REF
voltage). If the die
is the user's
PDS_USR
315
.