XC4VFX60-10FFG1152C Xilinx Inc, XC4VFX60-10FFG1152C Datasheet - Page 249

• Manufacturer Part Number: XC4VFX60-10FFG1152C
• Description: IC FPGA VIRTEX-4 FX 60K 1152FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX60-10FFG1152C

• Total Ram Bits: 4276224
• Number Of Logic Elements/cells: 56880
• Number Of Labs/clbs: 6320
• Number Of I /o: 576
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-BBGA, FCBGA
• No. Of Logic Blocks: 6656
• No. Of Macrocells: 56880
• Family Type: Virtex-4
• No. Of Speed Grades: 10
• No. Of I/o's: 576
• Clock Management: DCM
• Core Supply: RoHS Compliant
• Package: 1152FCBGA
• Family Name: Virtex®-4
• Device Logic Units: 56880
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 576
• Ram Bits: 4276224
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V4-ML410-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
OBUFTDS
IOBUFDS
Virtex-4 FPGA SelectIO Attributes/Constraints
R
Location Constraints
Figure 6-23
Figure 6-24
Access to some Virtex-4 FPGA I/O resource features (e.g., location constraints, input delay,
output drive strength, and slew rate) is available through the attributes/constraints
associated with these features. For more information a Constraints Guide is available on
the Xilinx website with syntax examples and VHDL/Verilog reference code. This guide is
available inside the Software Manuals at:
http://www.support.xilinx.com/support/software_manuals.htm
The location constraint (LOC) must be used to specify the I/O location of an instantiated
I/O primitive. The possible values for the location constraint are all the external port
identifiers (e.g., A8, M5, AM6, etc.). These values are device and package size dependent.
The LOC attribute uses the following syntax in the UCF file:
Example:
INST <I/O_BUFFER_INSTANTIATION_NAME> LOC =
"<EXTERNAL_PORT_IDENTIFIER>";
INST MY_IO LOC=R7;
Figure 6-23: Differential 3-state Output Buffer Primitive (OBUFTDS)
Figure 6-24: Differential Input/Output Buffer Primitive (IOBUFDS)
shows the differential 3-state output buffer primitive.
shows the differential input/output buffer primitive.
3-state Input
from FPGA
O (Output)
to FPGA
I (Input)
www.xilinx.com
T
3-state Input
Input from
FPGA
I
IOBUFDS
+
–
T
+
–
OBUFTDS
+
–
OB
O
Virtex-4 FPGA SelectIO Primitives
UG070_6_23_031108
Output to
Device Pads
IOB
IO
UG070_6_24_031108
I/O
to/from
Device Pad
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