XC4VFX60-10FFG1152C Xilinx Inc, XC4VFX60-10FFG1152C Datasheet - Page 371
XC4VFX60-10FFG1152C
Manufacturer Part Number
XC4VFX60-10FFG1152C
Description
IC FPGA VIRTEX-4 FX 60K 1152FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r
Datasheets
1.XC4VFX12-10FFG668C.pdf
(58 pages)
2.XC4VFX12-10FFG668C.pdf
(9 pages)
3.XC4VFX12-10FFG668C.pdf
(406 pages)
Specifications of XC4VFX60-10FFG1152C
Total Ram Bits
4276224
Number Of Logic Elements/cells
56880
Number Of Labs/clbs
6320
Number Of I /o
576
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-BBGA, FCBGA
No. Of Logic Blocks
6656
No. Of Macrocells
56880
Family Type
Virtex-4
No. Of Speed Grades
10
No. Of I/o's
576
Clock Management
DCM
Core Supply
RoHS Compliant
Package
1152FCBGA
Family Name
Virtex®-4
Device Logic Units
56880
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
576
Ram Bits
4276224
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
HW-V4-ML410-UNI-G - EVALUATION PLATFORM VIRTEX-4
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC4VFX60-10FFG1152C
Manufacturer:
XilinxInc
Quantity:
3 000
Company:
Part Number:
XC4VFX60-10FFG1152C
Manufacturer:
Xilinx Inc
Quantity:
10 000
- XC4VFX12-10FFG668C PDF datasheet
- XC4VFX12-10FFG668C PDF datasheet #2
- XC4VFX12-10FFG668C PDF datasheet #3
- Current page: 371 of 406
- Download datasheet (6Mb)
Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
R
Clock Event 2
The reset pulse is deasserted on the rising edge of CLKDIV. The difference in propagation
delay between the two ISERDES causes the SR input to come out of reset in two different
CLK cycles. If there were no internal re-timing, ISERDES1 would come out of reset one
CLK cycle before ISERDES0, which would leave both ISERDES out of sync.
Clock Event 3
The release of the reset signal at the SR input is re-timed internally to CLKDIV. This brings
ISERDES 0 and 1 back into sync.
Clock Event 4
The release of the reset signal at the SR input is re-timed internally to CLK.
Figure 8-5: Two ISERDES Coming Out of Reset Synchronously with One Another
Internal Reset
Internal Reset
(CLKDIV)
Signal at
SR Input
(CLK)
www.xilinx.com
ISERDES0
ISERDES1
ISERDES0
ISERDES1
ISERDES0
ISERDES1
CLKDIV
CLK
Input Serial-to-Parallel Logic Resources (ISERDES)
Event 1
Clock
Event 2
Clock
Event 3
Clock
Clock
Event 4
UG070_c8_21_041007
371
Related parts for XC4VFX60-10FFG1152C
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
IC FPGA VIRTEX-4 FX 60K 672-FBGA
Manufacturer:
Xilinx Inc
Part Number:
Description:
IC FPGA VIRTEX-4 FX 60K 672-FBGA
Manufacturer:
Xilinx Inc
Datasheet:
Part Number:
Description:
IC FPGA VIRTEX-4 FX 60K 672-FBGA
Manufacturer:
Xilinx Inc
Datasheet:
Part Number:
Description:
IC FPGA VIRTEX-4 FX 60K 1152FBGA
Manufacturer:
Xilinx Inc
Datasheet:
Part Number:
Description:
IC FPGA VIRTEX-4 FX 60K 1152FBGA
Manufacturer:
Xilinx Inc
Datasheet:
Part Number:
Description:
IC FPGA VIRTEX-4FX 1152FFBGA
Manufacturer:
Xilinx Inc
Datasheet:
Part Number:
Description:
IC FPGA VIRTEX-4FX 1152FFBGA
Manufacturer:
Xilinx Inc
Datasheet:
Part Number:
Description:
FPGA Virtex®-4 Family 56880 Cells 90nm (CMOS) Technology 1.2V 672-Pin FCBGA
Manufacturer:
Xilinx Inc
Datasheet:
Part Number:
Description:
IC FPGA VIRTEX-4 FX 60K 672-FBGA
Manufacturer:
Xilinx Inc
Datasheet:
Part Number:
Description:
IC FPGA VIRTEX-4 FX 60K 672-FBGA
Manufacturer:
Xilinx Inc
Datasheet:
Part Number:
Description:
IC FPGA VIRTEX-4 FX 60K 1152FBGA
Manufacturer:
Xilinx Inc
Datasheet:
Part Number:
Description:
FPGA Virtex®-4 Family 56880 Cells 90nm (CMOS) Technology 1.2V 672-Pin FCBGA
Manufacturer:
Xilinx Inc
Datasheet:
Part Number:
Description:
IC CPLD .8K 36MCELL 44-VQFP
Manufacturer:
Xilinx Inc
Datasheet:
Part Number:
Description:
IC CPLD 72MCRCELL 10NS 44VQFP
Manufacturer:
Xilinx Inc
Datasheet: