XC4VFX60-10FFG1152C Xilinx Inc, XC4VFX60-10FFG1152C Datasheet - Page 356

• Manufacturer Part Number: XC4VFX60-10FFG1152C
• Description: IC FPGA VIRTEX-4 FX 60K 1152FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX60-10FFG1152C

• Total Ram Bits: 4276224
• Number Of Logic Elements/cells: 56880
• Number Of Labs/clbs: 6320
• Number Of I /o: 576
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-BBGA, FCBGA
• No. Of Logic Blocks: 6656
• No. Of Macrocells: 56880
• Family Type: Virtex-4
• No. Of Speed Grades: 10
• No. Of I/o's: 576
• Clock Management: DCM
• Core Supply: RoHS Compliant
• Package: 1152FCBGA
• Family Name: Virtex®-4
• Device Logic Units: 56880
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 576
• Ram Bits: 4276224
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V4-ML410-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 7: SelectIO Logic Resources
356
SAME_EDGE Mode
Clock Forwarding
In SAME_EDGE mode, a third register (OFF3 or TFF3), clocked by a rising edge clock, is
placed on the input of the falling edge register. The output DDR registers and the signals
associated with the SAME_EDGE mode are shown in
Using this scheme, data can now be presented to the IOB on the same clock edge.
Presenting the data to the IOB on the same clock edge avoids setup time violations and
allows the user to perform higher DDR frequency with minimal register to register delay,
as opposed to using the CLB registers. The additional register is used to maintain an
alternating bits output of DATA_1 and DATA_2 on the DDR multiplexer.
shows the timing diagram of the output DDR using the SAME_EDGE mode.
Output DDR can forward a copy of the clock to the output. This is useful for propagating
a clock and DDR data with identical delays, and for multiple clock generation, where every
clock load has a unique clock driver. This is accomplished by tying the D1 input of the
ODDR primitive Low, and the D2 input High. Xilinx recommends using this scheme to
forward clocks from the FPGA fabric to the output pins.
CE
D1
D2
R
C
S
OQ
CE
D1
D2
C
Figure 7-24: Output DDR Timing in SAME_EDGE Mode
Figure 7-23: Output DDR in SAME_EDGE Mode
D
R
CE
D
R
CE
CLK
CLK
D1A
D2A
www.xilinx.com
S
S
D1A D2A D1B
Q
Q
D1B
D2B
D2B D1C D2C D1D
D1C
D2C
D
R
CE
CLK
Figure
S
UG070 (v2.6) December 1, 2008
7-23.
Q
D1D
D2D
Virtex-4 FPGA User Guide
UG070_7_24_031208
DDR MUX
Figure 7-24
UG070_7_23_031208
OQ
R