XC4VFX60-10FFG1152C Xilinx Inc, XC4VFX60-10FFG1152C Datasheet - Page 252

• Manufacturer Part Number: XC4VFX60-10FFG1152C
• Description: IC FPGA VIRTEX-4 FX 60K 1152FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX60-10FFG1152C

• Total Ram Bits: 4276224
• Number Of Logic Elements/cells: 56880
• Number Of Labs/clbs: 6320
• Number Of I /o: 576
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-BBGA, FCBGA
• No. Of Logic Blocks: 6656
• No. Of Macrocells: 56880
• Family Type: Virtex-4
• No. Of Speed Grades: 10
• No. Of I/o's: 576
• Clock Management: DCM
• Core Supply: RoHS Compliant
• Package: 1152FCBGA
• Family Name: Virtex®-4
• Device Logic Units: 56880
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 576
• Ram Bits: 4276224
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V4-ML410-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 6: SelectIO Resources
252
Verilog Template
--Example IOBUF instantiation
U_IOBUF : IOBUF
Port map(
O => user_o,
IO => user_io,
I => user_i,
T => user_t
);
//Example IOBUF module declaration
module IOBUF (O, IO, I, T);
endmodule
//Example IOBUF instantiation
IOBUF U_IOBUF (
.O(user_o),
.IO(user_io),
.I(user_i),
.T(user_t));
end component;
port(
parameter CAPACITANCE = "DONT_CARE";
parameter DRIVE = 12;
parameter IOSTANDARD = "LVCMOS25";
parameter SLEW = "SLOW";
output O;
inout
input
tri0 GTS = glbl.GTS;
or O1 (ts, GTS, T);
bufif0 T1 (IO, I, ts);
buf B1 (O, IO);
SLEW
);
O
IO : inout std_ulogic;
I
T
);
: out
: in
: in
IO;
I, T;
std_ulogic;
std_ulogic;
std_ulogic
www.xilinx.com
: string
:= "SLOW"
UG070 (v2.6) December 1, 2008
Virtex-4 FPGA User Guide
R