EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 70

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

4–10
Table 4–3. Input Register Modes
Multiplier and First-Stage Adder
Arria II GX Device Handbook, Volume 1
Parallel input
Shift register input
Loopback input
Notes to
(1) The multiplier operand input word lengths are statically configured at compile time.
(2) Available only on the A-operand.
(3) Only one loopback input is allowed per half block. For details, refer to
Register Input Mode
Table
4–3:
(3)
(2)
You must select the incoming data for multiplier input (A) from either general routing
or from the cascade chain at compile time. In cascade mode, the dedicated shift
outputs from one multiplier block directly feeds input registers of the adjacent
multiplier below it (in the same half-DSP block) or the first multiplier in the next
half-DSP block, to form an 8-tap shift register chain per DSP block. The DSP block can
increase the length of the shift register chain by cascading to the lower DSP blocks.
The dedicated shift register chain spans a single column, but you can implement
longer shift register chains requiring multiple columns using the regular FPGA
routing resources.
Shift registers are useful in DSP functions such as FIR filters. When implementing
18 × 18 or smaller width multipliers, you do not require external logic to create the
shift register chain because the input shift registers are internal to the DSP block. This
implementation significantly reduces the logical element (LE) resources required,
avoids routing congestion, and results in predictable timing.
The first multiplier in every half-DSP block (top- and bottom-half) in Arria II GX
devices has a multiplexer for the first multiplier B-input (lower-leg input) register to
select between general routing and loopback, as shown in
loopback mode, the most significant 18-bit registered outputs are connected as
feedback to the multiplier input of the first top multiplier in each half-DSP block.
Loopback modes are used by recursive filters where the previous output is required to
compute the current output.
Loopback mode is described in detail in
page
Table 4–3
The multiplier stage supports 9 × 9, 12 × 12, 18 × 18, or 36 × 36 multipliers. Other
word lengths are padded up to the nearest appropriate native wordlength; for
example, 16 × 16 would be padded up to use 18 × 18. For more information, refer to
“Independent Multiplier Modes” on page
multiplier, a single DSP block can perform many multiplications in parallel.
Each multiplier operand can be a unique signed or unsigned number. Two dynamic
signals, signa and signb, control the representation of each operand, respectively. A
logic 1 value on the signa/signb signal indicates that data A/data B is a signed
number; a logic 0 value indicates an unsigned number.
the multiplication result for the various operand sign representations. The result of
the multiplication is signed if any one of the operands is a signed value.
(1)
4–20.
lists the summary of input register modes for the DSP block.
9 × 9
v
—
—
12 × 12
v
—
—
Figure 4–12 on page
“Two-Multiplier Adder Sum Mode” on
4–13. Depending on the data width of the
18 × 18
v
v
v
4–21.
Chapter 4: DSP Blocks in Arria II GX Devices
Figure 4–4 on page
Table 4–4
36 × 36
DSP Block Resource Descriptions
© July 2010 Altera Corporation
v
—
—
lists the sign of
Double
v
—
—
4–7. In