EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 144

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

6–10
Programmable Pull-Up Resistor
Programmable Pre-Emphasis
Programmable Differential Output Voltage
MultiVolt I/O Interface
Arria II GX Device Handbook, Volume 1
f
f
Each Arria II GX device I/O pin provides an optional programmable pull-up resistor
during user mode. If you enable this feature for an I/O pin, the pull-up resistor
weakly holds the I/O to the V
Programmable pull-up resistors are only supported on user I/O pins and are not
supported on dedicated configuration pins, JTAG pins, or dedicated clock pins. If you
enable the programmable pull-up option, you cannot use the bus-hold feature.
Arria II GX LVDS transmitters support programmable pre-emphasis to compensate
the frequency dependent attenuation of the transmission line. The Quartus II software
allows two settings for programmable pre-emphasis control—0 and 1—where 0 is
pre-emphasis off and 1 is pre-emphasis on. The default setting is 1.
For more information about programmable pre-emphasis, refer to the
Differential I/O Interfaces with DPA in the Arria II GX Devices
Arria II GX LVDS transmitters support programmable V
settings allow you to adjust output eye height to optimize trace length and power
consumption. A higher V
while a smaller V
programmable V
For more information about programmable V
Interfaces with DPA in the Arria II GX Devices
Arria II GX architecture supports the MultiVolt I/O interface feature that allows
Arria II GX devices in all packages to interface with systems of different supply
voltages.
You can connect the VCCIO pins to a 1.2-, 1.5-, 1.8-, 2.5-, 3.0-, or 3.3-V power supply,
depending on the output requirements. The output levels are compatible with
systems of the same voltage as the power supply. (For example, when VCCIO pins are
connected to a 1.5-V power supply, the output levels are compatible with 1.5-V
systems).
You must connect the Arria II GX VCCPD power pins to a 2.5-, 3.0-, or 3.3-V power
supply. You can increase the performance of the output pins when you use these
power pins to supply pre-driver power to the output buffers.
Arria II GX MultiVolt I/O support.
OD
OD
to 2 when the programmable V
swing reduces power consumption. You can set the
OD
swing improves voltage margins at the receiver end,
CCIO
level.
chapter.
OD
, refer to the
OD
Chapter 6: I/O Features in Arria II GX Devices
is set to high.
OD
. Programmable V
chapter.
High-Speed Differential I/O
Table 6–5
© July 2010 Altera Corporation
Arria II GX I/O Structure
High-Speed
summarizes
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