EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 108

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

5–16
PLL Control Signals
Arria II GX Device Handbook, Volume 1
f
1
1
Arria II GX PLLs can also drive out to any regular I/O pin through the GCLK or
RCLK network. You can also use the external clock output pins as user I/O pins if you
do not require external PLL clocking. However, external clock output pins can
support a differential I/O standard that is only driven by PLL.
You can use the pfdena, areset, and locked signals to observe and control PLL
operation and resynchronization.
pfdena
Use the pfdena signal to maintain the most recent locked frequency to allow your
system to store its current settings before shutting down. The pfdena signal controls
the PFD output with a programmable gate. If you disable the PFD, the VCO operates
at its most recent set value of control voltage and frequency with some long-term drift
to a lower frequency.
areset
The areset signal is the reset or resynchronization input for each PLL. The device
input pins or internal logic can drive these input signals. When areset is driven
high, the PLL counters reset, clearing the PLL output and placing the PLL out-of-lock.
The VCO is then set back to its nominal setting. When areset is driven low again,
the PLL resynchronizes to its input as it relocks.
You must include the areset signal in designs if any of the following conditions are
true:
■
■
If the input clock to the PLL is not toggling or is unstable after power up, assert the
areset signal after the input clock is stable and in specifications.
locked
The locked signal indicates that the PLL has locked onto the reference clock and the
PLL clock outputs are operating at the desired phase and frequency set in the
Quartus II software.
Altera recommends using the areset and locked signals in your designs to control
and observe the status of your PLL.
For more information about the PLL control signals, refer to the
User
PLL reconfiguration or clock switchover is enabled in your design.
Phase relationships between the PLL input and output clocks must be maintained
after a loss-of-lock condition.
Guide.
Chapter 5: Clock Networks and PLLs in Arria II GX Devices
© July 2010 Altera Corporation
ALTPLL Megafunction
PLLs in Arria II GX Devices