EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet
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... Innovation Drive San Jose, CA 95134 www.altera.com AIIGX5V1-3.0 Arria II GX Device Handbook, Volume 1 ...
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... Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation ...
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... Arithmetic Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 Shared Arithmetic Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 LUT-Register Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 Register Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 ALM Interconnects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 Clear and Preset Logic Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 Chapter 3. Memory Blocks in Arria II GX Devices © July 2010 Altera Corporation Contents Arria II GX Device Handbook, Volume 1 ...
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... Two-Multiplier Adder Sum Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20 18 × 18 Complex Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21 Four-Multiplier Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22 High-Precision Multiplier Adder Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23 Multiply Accumulate Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-25 Shift Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-26 Rounding and Saturation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-28 DSP Block Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-30 Arria II GX Device Handbook, Volume 1 © July 2010 Altera Corporation ...
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... PLL Reconfiguration Hardware Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-31 Post-Scale Counters ( 5-32 Scan Chain Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-33 Charge Pump and Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-35 Bypassing PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-36 Dynamic Phase-Shifting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-36 PLL Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-38 Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-39 Section II. I/O Interfaces © July 2010 Altera Corporation v Arria II GX Device Handbook, Volume 1 ...
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... Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24 Chapter 7. External Memory Interfaces in Arria II GX Devices Arria II GX Memory Interfaces Pin Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 Combining ×16/×18 DQ/DQS Groups for ×36 QDR II+/QDR II SRAM Interface . . . . . . . . . . . . . . . 7-13 Rules to Combine Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13 Arria II GX Device Handbook, Volume 1 © July 2010 Altera Corporation ...
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... Setting Up an LVDS Transmitter or Receiver Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-33 Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-34 Section III. System Integration Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III-1 Chapter 9. Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices Configuration Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 © July 2010 Altera Corporation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-17 OD Arria II GX Device Handbook, Volume 1 vii ...
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... Remote System Upgrade Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-50 Remote System Upgrade Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-51 Remote System Upgrade Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-52 Remote System Upgrade State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-53 User Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-54 Quartus II Software Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-54 ALTREMOTE_UPDATE Megafunction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-55 Arria II GX Device Handbook, Volume 1 © July 2010 Altera Corporation ...
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... Insertion or Removal of an Arria II GX Device from a Powered-Up System . . . . . . . . . . . . . . . . . . 12-3 Hot Socketing Feature Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4 Additional Information About this Handbook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info-1 How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info-1 Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info-1 © July 2010 Altera Corporation ix Arria II GX Device Handbook, Volume 1 ...
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... Arria II GX Device Handbook, Volume 1 © July 2010 Altera Corporation ...
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... Part Number: AIIGX51009-3.0 Chapter 10 SEU Mitigation in Arria II GX Devices Revised: Part Number: AIIGX51010-3.0 Chapter 11 JTAG Boundary-Scan Testing Revised: Part Number: AIIGX51011-3.0 © July 2010 Altera Corporation Arria II GX Device Handbook, Volume July 2010 June 2009 November 2009 July 2010 July 2010 ...
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... Chapter 12 Power Requirements for Arria II GX Devices Revised: Part Number: AIIGX51012-2.0 Arria II GX Device Handbook, Volume 1 July 2010 Chapter Revision Dates © July 2010 Altera Corporation ...
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... Revision History Refer to each chapter for its own specific revision history. For information on when each chapter was updated, refer to the Chapter Revision Dates section, which appears in this volume. © July 2010 Altera Corporation Section I. Device Core II GX ® Arria II GX Device Handbook, Volume 1 ...
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... I–2 Arria II GX Device Handbook, Volume 1 Chapter : © July 2010 Altera Corporation ...
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... Physical Interface for PCI Express and DDR3 memory are easily implemented in your design with the Quartus software, the SOPC Builder design software, and a broad library of hard and soft intellectual property (IP) solutions from Altera designing for applications requiring transceivers operating 6.375 Gbps fast and easy. ...
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... Chapter 1: Arria II GX Device Family Overview Highlights 49,640 76,120 102,600 118,143 181,165 244,188 730 840 950 6,570 7,560 8,550 8,121 9,939 11,756 576 656 736 © July 2010 Altera Corporation ...
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... RX = True LVDS input buffers without True LVDS output buffers. (6) eTX = Emulated-LVDS output buffers, either LVDS_E_3R or LVDS_E_1R. (7) The LVDS channel count does not include dedicated clock input pins and PLL clock output pins. © July 2010 Altera Corporation EP2AGX45 EP2AGX65 EP2AGX95 EP2AGX125 EP2AGX190 EP2AGX260 ...
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... C4, C5, C6, I3 device family with a ® PLL Memory Interface High-Speed Differential I/O with DPA, General Purpose I/O, and Memory Interface PLL PLL High-Speed Differential I/O with DPA, General Purpose I/O, and Memory Interface PLL Memory Interface DLL © July 2010 Altera Corporation ...
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... Reverse serial loopback pre- and post-CDR to transmitter buffer for physical ■ link diagnostics Loopback master and slave capability in PCIe hard IP blocks ■ Support for protocol features such as MSB-to-LSB transmission in a ■ SONET/SDH configuration and spread-spectrum clocking in a PCIe configuration © July 2010 Altera Corporation 1–5 Arria II GX Device Handbook, Volume 1 ...
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... Arria II GX Device Handbook, Volume 1 Feature Descriptions Hard IP Data Link Layer and Transaction Layer Hard IP Data Link Layer and custom Soft IP Transaction Layer Arria II GX Transceiver Architecture Chapter 1: Arria II GX Device Family Overview Arria II GX Device Architecture chapter. © July 2010 Altera Corporation ...
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... The Quartus instantiating memory using a dedicated megafunction wizard or by inferring memory directly from VHDL or Verilog source code. © July 2010 Altera Corporation II software allows you to take advantage of M9K memory blocks by ® 1–7 Plug-In TM ...
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... Table 1–6 I/O Standard LVTTL, LVCMOS, SSTL, HSTL, PCIe, and PCI-X SSTL, HSTL, LVPECL, LVDS, mini-LVDS, Bus LVDS (BLVDS), and RSDS and V CCIO REF Arria II GX Device Architecture levels © July 2010 Altera Corporation ...
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... An auto-calibrating megafunction is available in the Quartus II software for DDR SDRAM, DDR2 SDRAM, and DDR3 SDRAM memory interface PHYs; the megafunction takes advantage of the PLL dynamic reconfiguration feature to calibrate based on the changes of process, voltage, and temperature (PVT). © July 2010 Altera Corporation 1–9 Arria II GX Device Handbook, Volume 1 ...
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... External Memory Interfaces in Arria II GX Devices Nios II ■ Arria II GX devices support all variants of the NIOS ■ Nios II processors are supported by an array of software tools from Altera and leading embedded partners and are used by more designers than any other configurable processor Configuration Features ■ ...
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... Figure 1–2. Packaging Ordering Information Arria II GX Devices Family EP2AGX Device Density 45, 65, 95 125, 190, 260 Transceiver Count F:16 Package Type F: FineLine BGA (FBGA) U: Micro BGA (UFBGA) © July 2010 Altera Corporation EP2AGX C Ball Array Dimension Corresponds to pin count 17 = 358 pins 25 = 572 pins 29 = 780 pins 35 = 1152 pins 1– ...
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... Updated Table 1–1, Table 1–2, and Table 1–3 ■ Updated “Configuration Features” section ■ Updated Table 1–2. ■ Updated “I/O Features” section. ■ Initial release. Chapter 1: Arria II GX Device Family Overview Document Revision History DPA”section © July 2010 Altera Corporation ...
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... R20 R4 Direct link interconnect from adjacent block Direct link interconnect to adjacent block Local Interconnect © June 2009 Altera Corporation 2. Logic Array Blocks and Adaptive Logic Modules in Arria II GX Devices C4 C12 Row Interconnects of Variable Speed & Length MLAB LAB Local Interconnect is Driven from Either Side by Column Interconnect & ...
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... LUT-based- ALM Simple dual port SRAM (1) LUT-based- ALM Simple dual port SRAM (1) LUT-based- ALM Simple dual port SRAM (1) LUT-based- ALM Simple dual port SRAM LUT-based- (1) ALM Simple dual port SRAM MLAB LAB Logic Array Blocks chapter in © June 2009 Altera Corporation ...
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... Figure 2–3. Direct Link Connection Direct link interconnect from left LAB, memory block, DSP block, or IOE output ALMs Direct link interconnect to left MLAB © June 2009 Altera Corporation Local Interconnect LAB 2–3 Direct link interconnect from right LAB, memory block, DSP block, or IOE output ALMs ...
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... Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Arria II GX Devices There are two unique clock signals per LAB. labclk0 labclk1 labclk2 labclkena0 labclkena1 labclkena2 or asyncload or labpreset Adaptive Logic Modules Figure 2–4. The labclr1 syncload labclr0 synclr Figure 2–5 shows a © June 2009 Altera Corporation ...
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... Figure 2–5. High-Level Block Diagram of the Arria II GX ALM shared_arith_in Combinational/Memory ALUT0 dataf0 datae0 6-Input LUT dataa datab datac datad 6-Input LUT datae1 dataf1 Combinational/Memory ALUT1 shared_arith_out © June 2009 Altera Corporation carry_in reg_chain_in labclk adder0 adder1 reg_chain_out carry_out 2–5 To general or local routing To general local routing ...
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... GND + + V CC carry_out Adaptive Logic Modules CLR local D Q interconnect row, column direct link routing row, column direct link routing CLR local D Q interconnect row, column direct link routing row, column direct link routing reg_chain_out © June 2009 Altera Corporation ...
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... Functions that fit into the template shown in “if-else” statements in Verilog HDL or VHDL code. © June 2009 Altera Corporation II software automatically configures the ALMs for optimized shows the template of supported seven-input functions utilizing Figure 2–7 2– ...
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... LUT D reg0 4-Input LUT adder1 4-Input LUT D 4-Input reg1 LUT carry_out Adaptive Logic Modules To general or local routing To general or Q local routing To general or local routing To general or Q local routing To general or local routing To general or Q local routing © June 2009 Altera Corporation ...
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... LAB within the column. In every alternate LAB column, the top half can be bypassed; in the other MLAB columns, the bottom half can be bypassed. 1 For more information on carry chain interconnect, refer to page 2–13. © June 2009 Altera Corporation 2–9 “ALM Interconnects” on Arria II GX Device Handbook, Volume 1 ...
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... ALM using this feature. shared_arith_in carry_in labclk 4-Input LUT D reg0 4-Input LUT 4-Input LUT D 4-Input reg1 LUT carry_out shared_arith_out Adaptive Logic Modules To general or local routing To general or Q local routing To general or local routing To general or Q local routing © June 2009 Altera Corporation ...
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... Figure 2–11 shows the ALM in LUT-Register mode. Figure 2–11. ALM in LUT-Register Mode with 3-Register Capability clk [2:0] aclr [1:0] DC1 © June 2009 Altera Corporation 2–13. shows the register constructed using two combinational blocks in 4-input LUT 5-input LUT reg_chain_in Third register datain ...
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... To general or local routing To general local routing reg0 To general local routing reg1 To general or local routing To general or local routing To general local routing reg0 To general local routing reg1 To general or local routing To next ALM in the LAB “ALM Interconnects” © June 2009 Altera Corporation ...
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... Table 2–1. Document Revision History Date and Document Version June 2009, v1.1 Updated Figure February 2009, v1.0 Initial Release. © June 2009 Altera Corporation Local interconnect routing among ALMs in the LAB ALM 1 Carry chain & shared arithmetic chain routing to adjacent ALM ...
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... Arria II GX Device Handbook, Volume 1 Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Arria II GX Devices Document Revision History © June 2009 Altera Corporation ...
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... Address clock enable Single-port memory Simple dual-port memory True dual-port memory Embedded shift register ROM © November 2009 Altera Corporation 3. Memory Blocks in Arria II GX Devices Plug-In Manager. You can stitch together multiple blocks of the same Feature MLABs 500 MHz 640 64 × × ...
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... M9K Blocks Outputs cleared Output registers Write and Read: Rising clock edges Outputs set to old data or new data Outputs set to old data or don’t care Soft IP support using Quartus II software 3,435 5,246 6,679 8,121 9,939 11,756 © November 2009 Altera Corporation ...
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... XXXX byteena XX 10 contents at a0 FFFF FFFF contents at a1 contents at a2 don't care: q (asynch) doutn doutn current data: q (asynch) © November 2009 Altera Corporation a1 a2 ABCD 01 11 ABFF FFFF ABXX XXCD ABCD ABFF FFCD ABCD XXXX XX FFCD ...
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... The default value for the address clock enable signals is low (disabled). Arria II GX Device Handbook, Volume ABCD ABFF FFFF FFFF FFCD FFFF ABFF ABCD Chapter 3: Memory Blocks in Arria II GX Devices Memory Features XXXX XX FFCD ABCD ABFF FFCD FFCD © November 2009 Altera Corporation ...
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... Figure 3–4. Arria II GX Address Clock Enable during Read Cycle Waveform inclock rdaddress a0 rden addressstall latched address an (inside memory) q (synch) doutn-1 doutn q (asynch) © November 2009 Altera Corporation 1 address[0] 0 address[0] register 1 address[N] register address[N] 0 addressstall clock a1 a2 ...
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... Figure 3–6. Arria II GX Address Clock Enable during Write Cycle Waveform for MLAB inclock a0 wraddress data 00 wren addressstall latched address an (inside memory) contents contents at a1 contents at a2 contents at a3 contents at a4 contents at a5 Arria II GX Device Handbook, Volume Chapter 3: Memory Blocks in Arria II GX Devices Memory Features © November 2009 Altera Corporation ...
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... To choose the desired read-during-write behavior, set the read-during-write behavior to either new data, old data, or don't care in the RAM MegaWizard Plug-In Manager in the Quartus II software. For more information about this behavior, refer to “Read-During-Write” on page © November 2009 Altera Corporation Guide. 3–17. Arria II GX Device Handbook, Volume 1 3–7 “ ...
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... MLABs 64 × × × × × × 20 Chapter 3: Memory Blocks in Arria II GX Devices Memory Modes q[] outclock “Packed M9K Blocks 8K × × × × × 9 512 × 16 512 × 18 256 × 32 256 × 36 © November 2009 Altera Corporation ...
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... MLAB. The read operation is triggered by the rising clock edges whereas the write operation is triggered by the falling clock edges. Figure 3–10. Timing Waveform for Read-Write Operations (Single-Port Mode) for MLAB clk_a wrena rdena address_a data_a q_a (asynch) © November 2009 Altera Corporation a0(old data a1(old data ...
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... Memory Modes rden q[ ] rdclock 1K×9 512×18 256×36 — — — — — — — — — — — — — — — — — — © November 2009 Altera Corporation ...
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... Arria II GX M9K blocks support true dual-port mode. Sometimes called bi-directional dual-port, this mode allows you to perform any combination of two port operations: two reads, two writes, or one read and one write at two different clock frequencies. Figure 3–14 shows the true dual-port RAM configuration. © November 2009 Altera Corporation ...
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... M9K block mixed-port width Write Port 8K×1 4K×2 2K×4 1K× — — — — — — — — © November 2009 Altera Corporation Memory Modes 512×16 1K×9 512×18 v — — v — — v — — v — — v — — — — ...
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... The size of a shift register (w × m × determined by the input data width (w), the length of the taps (m), and the number of taps (n). You can cascade memory blocks to implement larger shift registers. © November 2009 Altera Corporation dout0 ...
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... FIFO MegaWizard Plug-In Manager in the Quartus II software. Both single- and dual-clock (asynchronous) FIFOs are supported. f For more information about implementing FIFO buffers, refer to the DCFIFO Megafunctions User Arria II GX Device Handbook, Volume 1 Chapter 3: Memory Blocks in Arria II GX Devices Guide. © November 2009 Altera Corporation Memory Modes n Number of Taps SCFIFO and ...
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... An output clock controls the data output registers. Asynchronous clears are available on output latches and output registers only. © November 2009 Altera Corporation True Simple Single-Port ...
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... Therefore, you must implement conflict resolution logic, external to the memory block, to avoid address conflicts. Arria II GX Device Handbook, Volume 1 Chapter 3: Memory Blocks in Arria II GX Devices Design Considerations Logic Array Blocks and chapter. © November 2009 Altera Corporation ...
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... Figure 3–18. Same Port Read-During Write: New Data Mode clk_a address rdena wrena bytenna data_a q_a (asyn) © November 2009 Altera Corporation Figure 3–17 Port B data in Port B data out A123 B456 ...
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... B423 A1(old data) old old Guide. A0 AAAA BBBB CCCC DDDD AAAA A0 (old data) AABB A1(old data) Chapter 3: Memory Blocks in Arria II GX Devices Design Considerations A1 11 EEEE FFFF DDDD EEEE Figure 3– EEEE FFFF 11 A1 DDDD EEEE © November 2009 Altera Corporation ...
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... Figure 3–12, Figure 3–18, Figure 3–19, and Figure 3–20. Added Figure 3–2, Figure 3–6, Figure 3–10, and Figure 3–13. ■ February 2009, v1.0 Initial Release. © November 2009 Altera Corporation Handbook. Changes Made 3–2. 3–14. 3–19 RAM Megafunction User Guide ...
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... Arria II GX Device Handbook, Volume 1 Chapter 3: Memory Blocks in Arria II GX Devices Document Revision History © November 2009 Altera Corporation ...
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... Cascading 44-bit output bus to propagate output results from one block to the next ■ block without external logic support ■ Rich and flexible arithmetic rounding and saturation units ■ Efficient barrel shifter support © July 2010 Altera Corporation 4. DSP Blocks in Arria II GX Devices Arria II GX Device Handbook, Volume 1 ...
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... Four Precision Multiplier Multiplier Adder Mode Adder Mode 36 × × × 18 Multipliers 58 116 232 78 156 312 112 224 448 144 288 576 164 328 656 184 368 736 Figure 4–1 shows the 72 Output Data 72 Output Data © July 2010 Altera Corporation ...
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... You can configure the second-stage adders to provide the alternative functions shown in block. Equation 4–2. Four-Multiplier Adder Equation © July 2010 Altera Corporation and Figure 4–2. For all signed numbers, input and output data is P[36.. [17..0] × B [17..0] ± ...
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... W [43..0] ± n-1 provides a sum of four 18 × 18-bit multiplication operations Equation 4–3 provides a four 18 × 18-bit multiplication Figure 4–3. Detailed examples are described in Chapter 4: DSP Blocks in Arria II GX Devices Simplified DSP Operation [37..0] n Figure 4–3. © July 2010 Altera Corporation ...
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... Independent 18-bits 1 Multiplier 36-bits 1 Double 1 Two-Multiplier 18-bits 2 Adder (1) Four-Multiplier 18-bits 4 Adder Multiply 18-bits 4 Accumulate © July 2010 Altera Corporation From Previous Half-DSP Block Next Half-DSP Block # per Signed or RND, In Shift Block Unsigned SAT Register 8 Both Both Both Yes Yes ...
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... Chapter 4: DSP Blocks in Arria II GX Devices # per Signed or RND, In Shift Block Unsigned SAT Register 2 Both Both software automatically places ® DSP Block Resource Descriptions Chainout 1st Stage 2nd Stage Adder Add/Sub Add/Acc — — — No — Add Only © July 2010 Altera Corporation ...
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... The following DSP block signals control the input registers in the DSP block: ■ clock[3..0] ■ ena[3..0] ■ aclr[3..0] © July 2010 Altera Corporation lists the DSP block dynamic signals. signa signb zero_loopback accum_sload output_round zero_chainout output_saturate ...
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... Arria II GX Device Handbook, Volume 1 Chapter 4: DSP Blocks in Arria II GX Devices Figure 4–5. Table 4–9 on page 4–30 DSP Block Resource Descriptions shows a list of DSP block © July 2010 Altera Corporation ...
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... Note to Figure 4–5: (1) The scanina signal originates from the previous DSP block, while the scanouta signal goes to the next DSP block. © July 2010 Altera Corporation (Note 1) clock[3..0] ena[3..0] signa aclr[3..0] signb +/- +/- Delay Register scanouta 4– ...
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... Figure 4–12 on page 4–21. 4–13. Depending on the data width of the Chapter 4: DSP Blocks in Arria II GX Devices DSP Block Resource Descriptions Figure 4–4 on page 4– × 36 Double v v — — — — Table 4–4 lists the sign of © July 2010 Altera Corporation ...
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... The final stage of a 36-bit multiplier A sum of four (18 × 18) ■ An accumulator (44-bits maximum) ■ ■ A chained output summation (44-bits maximum) © July 2010 Altera Corporation Data B (signb Value) Unsigned (logic 0) Signed (logic 1) Unsigned (logic 0) Signed (logic 1) 4–20. Figure 4–4 on page 4– ...
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... The exception is when the block is used in shift mode, in which case you dynamically controls the output-select multiplexer directly. Arria II GX Device Handbook, Volume 1 Chapter 4: DSP Blocks in Arria II GX Devices DSP Block Resource Descriptions “Operational Mode Descriptions” on © July 2010 Altera Corporation ...
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... This is done by the Quartus II software by zero padding the LSBs. independent multiplier operation mode. A list of DSP block dynamic signals is shown in Table 4–9 on page © July 2010 Altera Corporation Figure 4–6, Figure 4–7, and Figure 4–8 4–30. ...
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... Note to Figure 4–6: (1) Block output for accumulator overflow and saturate overflow. Arria II GX Device Handbook, Volume 1 signa signb output_round output_saturate Half-DSP Block Chapter 4: DSP Blocks in Arria II GX Devices Operational Mode Descriptions overflow (1) 36 result_0 result_1[ ] © July 2010 Altera Corporation ...
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... Figure 4–7. 12-Bit Independent Multiplier Mode Shown for Half-DSP Block clock[3..0] ena[3..0] aclr[3..0] 12 dataa_0[11..0] 12 datab_0[11..0] 12 dataa_1[11..0] 12 datab_1[11..0] 12 dataa_2[11..0] 12 datab_2[11..0] © July 2010 Altera Corporation signa signb Half-DSP Block 4–15 24 result_0 result_1 result_2[ ] Arria II GX Device Handbook, Volume 1 ...
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... DSP block. 1 The round and saturation logic unit is supported for 18-bit independent multiplier mode only. Arria II GX Device Handbook, Volume 1 signa signb Half-DSP Block Chapter 4: DSP Blocks in Arria II GX Devices Operational Mode Descriptions 18 result_0 result_1 result_2 result_3[ ] © July 2010 Altera Corporation ...
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... Figure 4–9. 36-Bit Independent Multiplier Mode Shown for Half-DSP Block clock[3..0] ena[3..0] aclr[3..0] dataa_0[35..18] datab_0[35..18] dataa_0[17..0] datab_0[35..18] dataa_0[35..18] datab_0[17..0] dataa_0[17..0] datab_0[17..0] Half-DSP Block © July 2010 Altera Corporation Figure 4–9. signa signb + + + 4–17 72 result[ ] Arria II GX Device Handbook, Volume 1 ...
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... Figure 4–10 shows a 54 × 54-bit multiplier, which includes the special double-mode multiplier. Arria II GX Device Handbook, Volume 1 Chapter 4: DSP Blocks in Arria II GX Devices Operational Mode Descriptions © July 2010 Altera Corporation ...
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... July 2010 Altera Corporation signa signb Two Multiplier Adder Mode 36 + Double Mode Mode 72 Unsigned Multiplier 4–19 108 result[ ] Arria II GX Device Handbook, Volume 1 ...
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... The option to use the loopback mode or the general two-multiplier adder mode must be selected at compile time. Arria II GX Device Handbook, Volume 1 Chapter 4: DSP Blocks in Arria II GX Devices (Note 1) signa signb output_round output_saturate + Operational Mode Descriptions overflow (2) result[ ] Figure 4–12 © July 2010 Altera Corporation ...
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... DSP block. 18 × 18 Complex Multiplier You can configure the DSP block to implement complex multipliers using the two-multiplier adder mode. A single half-DSP block can implement one 18-bit complex multiplier. © July 2010 Altera Corporation signa signb ena[3..0] output_round aclr[3..0] ...
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... Arria II GX Device Handbook, Volume 1 shows how you can write a complex multiplication jb) × jd) = [(a × c) – (b × d)] + j[(a × × c)] and Equation 4–3 on page Chapter 4: DSP Blocks in Arria II GX Devices Operational Mode Descriptions Figure 4–13, the DSP block can 4–4. © July 2010 Altera Corporation ...
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... This can occur in cases where data has a high dynamic range. If the coefficients are fixed FFT and most filter applications, the precision of 18 bits provides a dynamic range over 100 dB, if the largest coefficient is normalized to the maximum 18-bit representation. © July 2010 Altera Corporation signa signb output_round output_saturate ...
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... Block output for accumulator overflow and saturate overflow. Arria II GX Device Handbook, Volume 1 Chapter 4: DSP Blocks in Arria II GX Devices [53.. C[17..0] × D[35..0] 1 signa signb + P 0 << <<18 Operational Mode Descriptions Figure 4–14, overflow (1) result[ ] © July 2010 Altera Corporation ...
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... Half-DSP Block Note to Figure 4–15: (1) Block output for saturation overflow of chainout. A single DSP block can implement up to two independent 44-bit accumulators. © July 2010 Altera Corporation Equation 4–3 on page 4–4. Figure 4–15 signa signb output_round output_saturate + + + 4– ...
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... Arria II GX Device Handbook, Volume 1 Chapter 4: DSP Blocks in Arria II GX Devices II processor to perform the dynamic shift and rotate ® shows the shift mode configuration. Table 4–5 lists examples of shift operations. Operational Mode Descriptions © July 2010 Altera Corporation ...
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... Signa Logical Shift Left Unsigned LSL[N] Logical Shift Right Unsigned LSR[32-N] Arithmetic Shift Left Signed ASL[N] Arithmetic Shift Right Signed ASR[32-N] Rotation ROT[N] Unsigned © July 2010 Altera Corporation signa signb rotate shift_right + + + Signb Shift Rotate A-input Unsigned 0 0 0×AABBCCDD Unsigned ...
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... Add to Integer Result 1 0110 0 0011 0 0010 1 0100 1 1110 0 1011 1 1110 0 1100 Round-To-Nearest-Even ➱ 010111 0110 ➱ 001101 0011 ➱ 001010 0010 ➱ 001110 0100 ➱ 110111 1110 101101 ➱ 1011 110110 ➱ 1110 ➱ 110010 1100 © July 2010 Altera Corporation ...
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... User defined SAT Positions (bit 43-28 For symmetric saturation, the RND bit position is also used to determine where the LSP for the saturated data is located. © July 2010 Altera Corporation – 1. Symmetrical saturation limits the (n– For example, for 32 bits: (n–1) Symmetric SAT Result 7FFFFFFFFh 800000001h 29 ...
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... Table 4–2 on page (A × B)], when used for an accumulation type of operation. (A × B)], when used for an accumulation type of operation. (A × B)]] Function Chapter 4: DSP Blocks in Arria II GX Devices Operational Mode Descriptions 4–5. However, for accumulation Count © July 2010 Altera Corporation ...
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... Input and Pipeline Register enable signals ena2 ena3 aclr0 aclr1 DSP block-wide asynchronous clear signals (active low) aclr2 aclr3 — Total Count per Half- and Full-DSP Blocks © July 2010 Altera Corporation Function Arria II GX Device Handbook, Volume 1 4–31 Count ...
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... Software Support for Arria II GX Devices Altera provides two distinct methods for implementing various modes of the DSP block in a design: instantiation and inference. Both methods use the following Quartus II megafunctions: ■ LPM_MULT ■ ALTMULT_ADD ALTMULT_ACCUM ■ ALTFP_MULT ■ You can instantiate the megafunctions in the Quartus II software to use the DSP block. ...
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... GCLK or RCLK networks. These clock pins are arranged on the three sides (top, bottom, and right sides) of the Arria II GX device, as shown in Figure 5–2. © July 2010 Altera Corporation 5. Clock Networks and PLLs in Arria Single-ended CLK[4..15] (6 Differential) CLK[4..15] pins, PLL clock outputs, ...
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... CLK[12..15] GCLK[12..15] GCLK[8..11] GCLK[4..7] CLK[4..7] shows CLK pins and PLLs that can drive RCLK networks in Clock Networks in Arria II GX Devices Figure 5–1 shows Top Right PLL PLL_2 (1) Center PLLs PLL_5 CLK[8..11] PLL_6 (1) PLL_3 Bottom Right PLL © July 2010 Altera Corporation ...
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... Arria II GX device. 1 The legal clock sources for PCLK networks are clock outputs from the DPA block, PLD-transceiver interface clocks, horizontal I/O pins, and internal logic. © July 2010 Altera Corporation CLK[12..15] RCLK[42..47] RCLK[36..41] RCLK[30..35] Q1 ...
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... Chapter 5: Clock Networks and PLLs in Arria II GX Devices Regional clock multiplexers PLL_3 Clock Networks in Arria II GX Devices Figure 5–3 Clock pins or PLL outputs can drive half of the device to create side-wide clocking regions for improved interface timing. © July 2010 Altera Corporation ...
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... GCLK[0..3] GCLK[4..7] GCLK[8..11] GCLK[12..15] Note to Table 5–2: (1) GCLK[0..3] is not driven by any clock pins because there are no dedicated clock pins on the left side of the Arria II GX device. © July 2010 Altera Corporation (PCIe ) through GCLK or RCLK networks. ® ® CLK (Pins ...
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... Table 5–5. The — — v — — — — — — © July 2010 Altera Corporation ...
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... When selecting the clock source dynamically, you can either select two PLL outputs (such C1 combination of clock pins or PLL outputs. © July 2010 Altera Corporation — — ...
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... CLK Outputs (3) Pin 2 CLKSELECT[1..0] (1) This multiplexer supports user-controllable dynamic switching Enable/ Disable GCLK Description through Table 5–6 on page 5–7. Clock Networks in Arria II GX Devices Inter-Transceiver Block Clock Lines (4) Internal Logic Static Clock Select (2) Internal Logic © July 2010 Altera Corporation ...
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... You can choose from among these inputs with the CLKSELECT[1..0]signal. For the connections between the PLL counter outputs to the clock control block on the left side of the Arria II GX device, refer to © July 2010 Altera Corporation CLK Pin PLL Counter ...
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... Chapter 5: Clock Networks and PLLs in Arria II GX Devices PLL Counter Outputs and m Counter 8 Static Clock Select Enable/ Disable Internal Logic IOE (2) Internal Logic Static Clock Select (1) PLL<#>_CLKOUT pin (1) ( Clock Networks in Arria II GX Devices (1) GCLK/ RCLK/ PLL_<#>_CLKOUT (1) © July 2010 Altera Corporation ...
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... This feature is useful for applications that require a low power or sleep mode. The clkena signal can also disable clock outputs if the system is not tolerant of frequency over-shoot during resynchronization. © July 2010 Altera Corporation Figure 5–8 shows a waveform example for the clock Arria II GX Device Handbook, Volume 1 ...
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... Arria II GX Device Handbook, Volume 1 Chapter 5: Clock Networks and PLLs in Arria II GX Devices Figure Clock Control Block (ALTCLKCTRL) Megafunction User 4 CLK[n+3..n] (2) 4 Arria II GX Transceiver Clocking chapter. Clock Networks in Arria II GX Devices 5–9. (1) inclk0 To the clock switchover block (1) inclk1 © July 2010 Altera Corporation ...
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... PLL cascading Compensation modes PLL drives DIFFCLK and LOADEN VCO output drives DPA clock Phase shift resolution Programmable duty cycle Output counter cascading © July 2010 Altera Corporation Arria II GX Device Family Overview chapter. Feature 512 1 single-ended or 1 differential pair (1) 3 single-ended or 3 differential pairs ...
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... Casade output to adjacent PLL /2, /4 ÷C0 GCLKs 8 ÷C1 ÷2 RCLKs 8 (2) External clock ÷C2 outputs DIFFCLK from ÷C3 Right PLLs LOAD_EN from Right PLLs (1) ÷Cn External ÷m memory interface DLL External clock outputs DIFFCLK network GCLK/RCLK network © July 2010 Altera Corporation ...
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... LVPECL, differential high-speed transceiver logic (HSTL), and differential SSTL determine which I/O standards are supported by the PLL clock input and output pins, refer to the © July 2010 Altera Corporation Internal Logic clkena1 (3) PLL<#>_CLKOUT<#>n (1), (2) Figure 5–11. Therefore, one counter or frequency I/O Features in Arria II GX Devices 5– ...
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... PLL clock outputs are operating at the desired phase and frequency set in the Quartus II software. 1 Altera recommends using the areset and locked signals in your designs to control and observe the status of your PLL. f For more information about the PLL control signals, refer to the User Guide ...
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... This mode is recommended for source-synchronous data transfers. Data and clock signals at the IOE experience similar buffer delays as long as you use the same I/O standard. © July 2010 Altera Corporation Clock Feedback Mode (1) 5–17 Table 5–9 ...
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... Arria II GX Device Handbook, Volume 1 Chapter 5: Clock Networks and PLLs in Arria II GX Devices Data pin PLL reference clock at input pin Data at register Clock at register Figure 5–13. Thus, this mode ideally compensates for PLLs in Arria II GX Devices © July 2010 Altera Corporation ...
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... Register Clock Port (1) External PLL Clock Outputs (1) Note to Figure 5–14: (1) The PLL clock outputs can lag the PLL input clocks depending on routine delays. © July 2010 Altera Corporation Data pin PLL reference clock at input pin Data at register Clock at register Phase Aligned ...
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... Arria II GX Device Handbook, Volume 1 Chapter 5: Clock Networks and PLLs in Arria II GX Devices Figure 5–15 Phase Aligned PLL Reference Clock at the Input Pin PLL Clock at the Register Clock Port PLLs in Arria II GX Devices shows an example waveform of the © July 2010 Altera Corporation ...
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... The Quartus II software automatically chooses the appropriate scaling factors according to the input frequency, multiplication, and division values entered into the ALTPLL megafunction. © July 2010 Altera Corporation Phase Aligned PLL Reference Clock at the Input Pin Dedicated PLL (M/N) ...
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... Arria II GX Device Handbook, Volume 1 Chapter 5: Clock Networks and PLLs in Arria II GX Devices VCO Output C0 C1 VCO Output C2 VCO Output C3 VCO Output C4 VCO Output Cn VCO Output PLLs in Arria II GX Devices Figure 5–17. from preceding post-scale counter (1) © July 2010 Altera Corporation ...
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... CLK1 signal is also divided by four. In this case, the two clocks are offset by 3 CLK2 is based off the 0phase from the VCO but has the C value for the counter set to three. This arrangement creates a delay of 2 © July 2010 Altera Corporation Φ ...
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... PLL input jitter tolerance specification. Arria II GX devices cannot internally generate spread-spectrum clocks. Arria II GX Device Handbook, Volume 1 Chapter 5: Clock Networks and PLLs in Arria II GX Devices t VCO ™ PLLs in Arria II GX Devices Plug-In Manager in the Quartus II © July 2010 Altera Corporation ...
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... You can select a clock source as the backup clock by connecting it to the inclk1 port of the PLL in your design. Figure 5–19. Automatic Clock Switchover Circuit Block Diagram inclk0 inclk1 muxout © July 2010 Altera Corporation Switchover Clock State Sense Machine clksw ...
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... PLL may lose lock after the switchover is completed and requires time to relock. 1 Altera recommends resetting the PLL with the areset signal to maintain the phase relationships between the PLL input and output clocks when you use clock switchover. ...
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... PLL reference, and the activeclock signal changes to indicate which clock is currently feeding the PLL. © July 2010 Altera Corporation (1) Plug-In Manager interface notifies you if a given combination of 5–27 Arria II GX Device Handbook, Volume 1 ...
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... Arria II GX Device Handbook, Volume 1 Chapter 5: Clock Networks and PLLs in Arria II GX Devices PLLs in Arria II GX Devices (Note 1) © July 2010 Altera Corporation ...
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... Wait for the locked signal to assert and become stable before reenabling the output clocks from the PLL at the clock control block. © July 2010 Altera Corporation n Counter muxout refclk 5–29 ...
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... Chapter 5: Clock Networks and PLLs in Arria II GX Devices shows how the VCO frequency gradually decreases when the current Switchover Occurs ) delays in real time by changing the PLL output clock phase shift. CO PLLs in Arria II GX Devices VCO Tracks Secondary Clock © July 2010 Altera Corporation ...
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... This figure shows the corresponding scan register for the K counter in between the scan registers for the charge pump and loop filter. The K counter is physically located after the VCO. 1 The counter settings are updated synchronously to the clock frequency of the individual counters. Therefore, all counters are not simultaneously updated. © July 2010 Altera Corporation PFD LF/K/CP (3) VCO /C2 /C1 ...
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... Arria II GX Device Handbook, Volume 1 Chapter 5: Clock Networks and PLLs in Arria II GX Devices 1 through 5 to reconfigure the PLL any number of times. PLLs in Arria II GX Devices D0 D0_old Dn © July 2010 Altera Corporation ...
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... Arria II GX PLLs have a 180-bit scan chain. component of an Arria II GX PLL. Table 5–10. Arria II GX PLL Reprogramming Bits (Part ( Charge Pump Current VCO Post-Scale divider (K) Loop Filter Capacitor © July 2010 Altera Corporation Table 5–10 Block Name Counter (3) 0 lists the number of bits for each ...
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... LB LB DATAOUT 0 1 Arria II GX Device Handbook, Volume 1 Chapter 5: Clock Networks and PLLs in Arria II GX Devices Block Name Counter 0 0 — LSB PLLs in Arria II GX Devices Number of Bits Total Other ( — 180 DATAIN rbypass 7 LB rselodd 7 © July 2010 Altera Corporation ...
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... Arria II GX PLLs. Table 5–11. charge_pump_current Bit Settings CP[ Table 5–12. loop_filter_r Bit Settings LFR[ Table 5–13. loop_filter_c Bit Settings LFC[1] © July 2010 Altera Corporation Table 5–11 through Table 5–13 CP[1] CP[ LFR[3] LFR[2] LFR[1] LFR[ ...
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... Logic array or I/O pin Logic array or I/O pin PLLs in Arria II GX Devices Description (1) PLL counter bypassed PLL counter not bypassed because (1) bit 8 (MSB) is set to 0 Guide. Source Destination PLL reconfiguration circuit PLL reconfiguration circuit PLL reconfiguration circuit © July 2010 Altera Corporation ) CO ...
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... VCO frequency is set to 1,000 MHz and the output clock frequency is set to 100 Mhz, performing 40 dynamic phase shifts (each one yields 125 ps phase shift) results in shifting the output clock by 180°, in other words, a phase shift of 5 ns. © July 2010 Altera Corporation Description GCLK, RCLK, or I/O pin ...
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... Arria II GX Device Handbook, Volume 1 Chapter 5: Clock Networks and PLLs in Arria II GX Devices Figure c ) may be greater than or less than one scanclk cycle. Phase Locked-Loops Reconfiguration (ALTPLL_RECONFIG) Guide. PLLs in Arria II GX Devices Figure 5–28, 5–28), the values of phaseupdown d Arria II GX Devices © July 2010 Altera Corporation ...
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... June 2009 1.1 ■ ■ ■ February 2009 1.0 Initial release © July 2010 Altera Corporation Changes Made Updated “Clocking Regions” and “Arria II GX PLL Hardware Overview” Updated Figure 5–28. Removed sub-regional clock references. Minor text edit. ...
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... Arria II GX Device Handbook, Volume 1 Chapter 5: Clock Networks and PLLs in Arria II GX Devices Document Revision History © July 2010 Altera Corporation ...
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... Revision History Refer to each chapter for its own specific revision history. For information on when each chapter was updated, refer to the Chapter Revision Dates section, which appears in this volume. © July 2010 Altera Corporation Section II. I/O Interfaces II GX device I/O features, external ® ...
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... II–2 Arria II GX Device Handbook, Volume 1 Chapter : © July 2010 Altera Corporation ...
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... Programmable pull-up resistor ■ Open-drain output ■ On-chip series termination (R On-chip differential termination (R ■ Programmable pre-emphasis ■ ■ Programmable voltage output differential (V © July 2010 Altera Corporation 6. I/O Features in Arria II GX Devices OCT) S OCT Arria II GX Device Handbook, Volume ® ...
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... CCPD Arria II GX © July 2010 Altera Corporation ...
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... graphical representation only. (7) The PLL_CLKOUT pin supports only emulated differential I/O standard but not true differential I/O standard. © July 2010 Altera Corporation (Note 1), (2), (3), (4), (5), (6), ...
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... July 2010 Altera Corporation ...
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... Programmable bus-hold ■ Programmable pull-up resistor Open-drain output ■ R OCT with or without calibration ■ S ■ R OCT D ■ PCI clamping diode © July 2010 Altera Corporation Device EP2AGX65 EP2AGX95 EP2AGX125 EP2AGX190 EP2AGX260 144 — — 12 — — 4 — — 240 248 ...
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... To ensure device reliability and proper operation when interfacing with a 3.3-V I/O system with Arria II GX devices important to ensure that the absolute maximum ratings are not violated. Altera recommends performing IBIS simulation to determine that the overshoot and undershoot voltages are in the guidelines. There are several techniques that you can use to limit overshoot and undershoot voltages, though none are required ...
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... Data realignment circuitry ■ Dynamic phase aligner (DPA) Synchronizer (FIFO buffer) ■ Phase-locked loops (PLLs) ■ © July 2010 Altera Corporation OCT for all LVTTL/LVCMOS S to 3.0 V, you can reduce overshoot and CCIO Arria II GX Devices Datasheet. chapter. Arria II GX Device Handbook, Volume 1 6– ...
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... HSTL/SSTL Class I I/O standards. The default setting is 25- R for HSTL/SSTL Class II I/O standards. (2) The default current strength setting in the Quartus II software is the current strength shown in brackets []. 1 Altera recommends performing IBIS or SPICE simulations to determine the right current strength setting for your specific application. Arria II GX Device Handbook, Volume 1 chapter. ...
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... I/O standards except for 3.3-V LVTTL/LVCMOS. You can use faster slew rates to improve the available timing margin in memory-interface applications or when the output pin has high-capacitive loading. Altera recommends performing IBIS or SPICE simulations to determine the right slew rate setting for your specific application. Open-Drain Output Arria II GX devices provide an optional open-drain output (equivalent to an open collector output) for each I/O pin ...
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... OD swing reduces power consumption. You can set the when the programmable refer to the OD chapter. Chapter 6: I/O Features in Arria II GX Devices Arria II GX I/O Structure High-Speed chapter. . Programmable set to high. High-Speed Differential I/O Table 6–5 summarizes © July 2010 Altera Corporation ...
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... I/O standard is not supported when V CCIO output operations are only supported when V (3) Altera recommends using an external clamp diode on the column I/O pins when the input signal is 3 3.3 V. Arria II GX OCT Support Arria II GX devices feature R termination capabilities. OCT maintains signal quality, saves board space, and reduces external component costs ...
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... OCT with calibration in all banks. The R S Figure 6–4 is the intrinsic impedance of transistors. Calibration Arria II GX Driver Series Termination V CCIO GND Chapter 6: I/O Features in Arria II GX Devices Arria II GX OCT Support Receiving Device ). TT OCT S Receiving Device © July 2010 Altera Corporation ...
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... HSTL-12 Class I HSTL-12 Class II LVDS Input On-Chip Differential Termination All I/O banks in Arria II GX devices support input R value of 100 , as shown in support R OCT. You can enable R D Figure 6–5. Differential Input On-Chip Termination © July 2010 Altera Corporation R S Right I/O ( ...
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... I/O bank that contains the block. CCIO can share one OCT calibration block, even if CCIO Guide. ). The reference voltage of the receiving device tracks the TT Figure 6–6 Arria II GX OCT Calibration voltage CCIO ALT_OCT ) and a REF shows the details of SSTL © July 2010 Altera Corporation ...
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... HSTL Class I Arria Ω External On-Board Termination 50 Ω V REF Transmitter Arria Ω Series OCT 50 Ω 50 Ω Series OCT Transmitter © July 2010 Altera Corporation Arria Transmitter Receiver Arria Ω Series OCT Receiver Transmitter Arria II GX Transmitter Receiver V TT Arria Ω Series OCT V ...
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... Transmitter Chapter 6: I/O Features in Arria II GX Devices Arria II GX Termination Schemes for I/O Standards Figure 6–8 through Differential SSTL Class Ω 50 Ω 50 Ω 50 Ω 25 Ω 50 Ω 25 Ω 50 Ω Receiver Ω 50 Ω Ω Ω 50 Ω Ω Receiver © July 2010 Altera Corporation ...
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... V LVDS requires a 100- termination resistor between the two signals at the input buffer. Arria II GX devices provide an optional 100- differential termination resistor in the device with R 700 Mbps. © July 2010 Altera Corporation 50 Ω Arria II GX Receiver Transmitter ...
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... AC-coupled termination scheme. The 50- resistors 0.1 μ Ω ICM = 50 Ω 0.1 μF Differential Inputs Differential Inputs 100 Ω Arria II GX OCT Differential Inputs 100 Ω Arria II GX OCT Arria II GX LVPECL Input Buffer 50 Ω 50 Ω © July 2010 Altera Corporation ...
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... A resistor network is required to attenuate the LVDS output-voltage swing to meet RSDS specifications. You can modify the three-resistor network values to reduce power or improve the noise margin. The resistor values chosen should satisfy the equation shown in © July 2010 Altera Corporation = 50 Ω Ω ...
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... Equation 6– validate that custom resistor values meet the RSDS requirements, Altera recommends performing additional simulations with IBIS models. f For more information about the RSDS I/O standard, refer to the RSDS Specification from the National Semiconductor website at www.national.com. mini-LVDS Arria II GX devices support the mini-LVDS output standard with a data rate up to 400 Mbps with LVDS-type output buffers ...
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... The resistor values chosen should satisfy the equation shown in Equation 6– validate that custom resistor values meet the RSDS requirements, Altera recommends performing additional simulations with IBIS models. f For more information about the mini-LVDS I/O standard, see the mini-LVDS Specification from the Texas Instruments website at www ...
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... Because an I/O bank can only have one V CCIO setting can support 2.5-V standard inputs and outputs CCIO voltage level at a given time. REF . CCIO Chapter 6: I/O Features in Arria II GX Devices Arria II GX Design Considerations impedance S and PCBs. CCIO CCIO CCIO © July 2010 Altera Corporation ...
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... Arria II GX devices and includes essential information for designing systems with an Arria II GX device’s selectable I/O capabilities. 3.3-V, 3.0-V, and 2.5-V LVTTL/LVCMOS Tolerance Guidelines Altera recommends the following techniques when you use 3.3-, 3.0-, and 2.5-V I/O standards to limit overshoot and undershoot at I/O pins: ■ ...
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... Voltage”, “Mini-LVDS”, “RSDS”, “OCT Calibration Block”, and “I/O Placement Guidelines” sections. Updated Figure 6–1, Figure 6–6, Figure 6–7, Figure 6–8, Figure 6–9, Figure 6–10, and Figure 6–14. Chapter 6: I/O Features in Arria II GX Devices Document Revision History 6–6. © July 2010 Altera Corporation ...
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... UniPHY IP core support for Arria II GX devices, refer to the External Memory Interface f For more information about the Arria II GX PLL, refer to the in Arria II GX Devices © July 2010 Altera Corporation 7. External Memory Interfaces devices that facilitate ® chapter. Handbook. ...
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... DDR Output and Output Enable Registers 2 DDR Output and Output Enable Registers Arria II GX Memory Interfaces Pin Support Memory Arria II GX FPGA DQS (Read) ( (Read) ( (Write) (4) DQS (Write) ( and t in DDR3, DQSS DSS DSH Section I. Device and © July 2010 Altera Corporation ...
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... Arria II GX I/O bank that does not support transceivers. All memory interface pins support the I/O standards required to support DDR3, DDR2, DDR SDRAM, and QDR II+/QDR II SRAM devices. © July 2010 Altera Corporation Figure 7–2). The Arria II GX pins marked with ...
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... Figure 7–9 show the maximum number of DQ/DQS groups per Guidelines. Number of I/O Module ×4 ( Arria II GX Memory Interfaces Pin Support Maximum Number of of Data Pins per Group Number of DQ/DQS Groups ×8/×9 ×16/×18 ×32/× © July 2010 Altera Corporation (1) ...
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... Several configuration pins in Bank 6A are shared with DQ/DQS pins. You cannot use a 4 DQ/DQS group with any of its pin members used for configuration purposes. Ensure that the DQ/DQS groups you have chosen are not also used for configuration. (3) Arria II GX devices in the 358-pin Ultra FineLine BGA package do not support 36 QDR II+/QDR II SRAM interface. © July 2010 Altera Corporation Number of I/O Module × ...
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... EP2AGX45 and EP2AGX65 ×32/×36=0 I/O Bank 5A 50 User I/Os ×4=6 ×8/×9=3 ×16/×18=1 ×32/×36=0 I/O Bank 4A 38 User I/Os ×4=4 ×4=4 ×8/×9=2 ×8/×9=2 ×16/×18=1 ×32/×36=0 Arria II GX Memory Interfaces Pin Support © July 2010 Altera Corporation ...
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... Ensure that the DQ/DQS groups you have chosen are not also used for configuration. (3) Arria II GX devices in the 572-pin FineLine BGA Package do not support 36 QDR II+/QDR II SRAM interface. © July 2010 Altera Corporation I/O Bank 7A 38 User I/Os × ...
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... EP2AGX45 and EP2AGX65 ×32/×36=0 I/O Bank 5A 66 User I/Os ×4=8 ×8/×9=4 ×16/×18=2 ×32/×36=1 I/O Bank 4A 70 User I/Os ×4=8 ×4=6 ×8/×9=4 ×8/×9=3 ×16/×18=2 ×32/×36=1 Arria II GX Memory Interfaces Pin Support © July 2010 Altera Corporation ...
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... Several configuration pins in Bank 6A are shared with DQ/DQS pins. You cannot use a 4 DQ/DQS group with any of its pin members used for configuration purposes. Ensure that the DQ/DQS groups you have chosen are not also used for configuration. © July 2010 Altera Corporation 1), ...
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... Arria II GX Memory Interfaces Pin Support I/O Bank 6A 66 User I/Os ×4=8 ×8/×9=4 ×16/×18=2 ×32/×36=1 I/O Bank 5A 66 User I/Os ×4=8 ×8/×9=4 ×16/×18=2 ×32/×36=1 © July 2010 Altera Corporation ...
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... The DQS and DQSn pins are listed in the Arria II GX pin tables as DQSXY and DQSnXY, respectively, where X denotes the DQ/DQS grouping number and Y denotes whether the group is located on the top (T), bottom (B), or right (R) side of the device. The DQ/DQS pin numbering is based on ×4 mode. © July 2010 Altera Corporation I/O Bank 8A I/O Bank 7B I/O Bank 7A ...
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... Chapter 7: External Memory Interfaces in Arria II GX Devices Figure 7–10 Figure 7–10 shows how the DQ/DQS groups are numbered in a die-top Arria II GX Device Arria II GX Memory Interfaces Pin Support for illustrations. DQS24T PLL2 7B DQS1R 6B 6A PLL5 PLL6 5A 5B DQS24R 4B PLL3 DLL1 DQS1B © July 2010 Altera Corporation ...
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... Altera recommends forming two ×36 groups on column I/O banks (top and bottom) only, although forming a × ...
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... This section describes each Arria II GX device feature that is used in external memory interfaces from the DQS phase-shift circuitry and DQS logic block you use the Altera memory controller MegaCore megafunction and UniPHY IP core are instantiated for you. f For more information about supported external memory IPs, refer to Section III: External Memory Interface System Specification Memory Handbook ...
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... DQS phase shift for different sides of the device. the DQS phase-shift circuitry is connected to the DQS/CQ and CQn pins in the device where memory interfaces are supported on the top, bottom, and right sides of the Arria II GX device. © July 2010 Altera Corporation 7–15 Figure 7–11 shows how ...
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... Pin “DLL” on page 7–17. Arria II GX External Memory Interface Features DQS Logic Blocks to Δt CQn IOE Pin to DQS/CQ Δt IOE Pin to Δt CQn IOE Pin to Δt DQS/CQ IOE Pin 6 DQS Phase-Shift Circuitry DLL Reference Clock (2) © July 2010 Altera Corporation ...
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... If you have a dedicated PLL that only generates the DLL input reference clock, set the PLL mode to No Compensation or the Quartus II software automatically changes it. Because the PLL does not use any other outputs, it does not have to compensate for any clock paths. © July 2010 Altera Corporation Table 7–4. Arria II GX Device Handbook, Volume 1 ...
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... CLK4 to CLK7 are located on the bottom side, CLK8 to CLK11 are located on the right side, and CLK12 to CLK15 are located on the top side of the device you are using the ALTMEMPHY megafunction or UniPHY IP core, Altera recommends using the dedicated PLL input pin for the PLL reference clock. Figure 7–12 shows a simple block diagram of the DQS phase-shift circuitry ...
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... DQS delay settings vary with PVT to implement the phase-shift delay. In frequency modes 4 and 5, only 5 bits of the DQS delay settings vary with PVT to implement the phase-shift delay; the MSB of the DQS delay setting is set to 0. © July 2010 Altera Corporation (Note 1) offsetdelayctrlin [5:0] offsetdelayctrlout [5:0] ...
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... Chapter 7: External Memory Interfaces in Arria II GX Devices Arria II GX External Memory Interface Features Available Phase Shift Number of Delay Chains 22.5, 45, 67.5, 90 30, 60, 90, 120 36, 72, 108, 144 45, 90, 135, 180 30, 60, 90, 120 36, 72, 108, 144 Arria II GX Devices © July 2010 Altera Corporation Datasheet. Arria II GX ...
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... The input reference clock for the DQS phase-shift circuitry can come from a PLL output clock or an input clock pin. For the exact PLL and input clock pin, refer to Table 7–4 on page 7–18 (2) The dqsenable signal can also come from the Arria II GX FPGA fabric. © July 2010 Altera Corporation DQS Enable dqsin <phase_setting> ...
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... Update Enable Circuitry Output Arria II GX Device Handbook, Volume 1 Chapter 7: External Memory Interfaces in Arria II GX Devices Arria II GX External Memory Interface Features Figure 7–14 shows an example waveform DLL Counter Update (Every 8 cycles) 6 bit © July 2010 Altera Corporation ...
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... Figure 7–16 shows the registers available in the Arria II GX input path. The input path consists of DDR input registers and resynchronization registers. You can bypass each block of the input path. © July 2010 Altera Corporation Figure 7–15. Postamble glitch Postamble Preamble ...
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... PLL. The outputs of the resynchronization registers go straight to the core. Arria II GX Device Handbook, Volume 1 Chapter 7: External Memory Interfaces in Arria II GX Devices (Note 1) Synchronization Registers regouthi D Q DFF I regoutlo neg_reg_out DFF DFF Input Reg Arria II GX External Memory Interface Features To Core (rdata0) To Core (rdata1) © July 2010 Altera Corporation ...
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... The output path is designed to route combinatorial or registered single data rate (SDR) outputs and DDR outputs from the FPGA core. The output enable path has a structure similar to the output path. You can have a combinatorial or registered output in SDR applications. © July 2010 Altera Corporation (Note 1) Double Data Rate Output-Enable Registers DFF ...
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... Arria II GX Device Handbook, Volume 1 Chapter 7: External Memory Interfaces in Arria II GX Devices Changes Made “Arria II GX Memory Interfaces Pin Support” Section I. Device and Pin Planning in volume 2 of the External Memory Interface Revision History section by adding reference to © July 2010 Altera Corporation ...
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... Reduced swing differential signaling (RSDS) ■ Low-voltage positive emitter-coupled logic (LVPECL) ■ Bus LVDS (BLVDS) © July 2010 Altera Corporation 8. High-Speed Differential I/O Interfaces and DPA in Arria II GX Devices II GX devices. The new modular I/O architecture ® .” on page 8–17 OD ...
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... I/O Features in Arria II GX Devices Datasheet. OCT) support. You can configure the LVDS I/O buffers as D OCT) or true LVDS output buffers. Alternatively, you D and V to 2.5 V. CCIO CCPD LVDS Channels chapter. OCT enabled, you must D I/O Features in Arria II GX Devices © July 2010 Altera Corporation ...
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... This is a top view of the silicon die, which corresponds to a reverse view for flip chip packages graphical representation only. (2) Applicable to EP2AGX95, EP2AGX125, EP2AGX190, and EP2AGX260 devices. (3) There are no center PLLs on the right I/O banks for EP2AGX45 and EP2AGX65 devices. © July 2010 Altera Corporation High-Speed Differential I/O, General Purpose I/O, General Purpose I/O, ...
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... TX or eTX) OCT support. LVDS Channels OCT and D 1), (2), (3), (4), (5), (6) 1152-Pin FlipChip FBGA — — 32(RD or eTX) + 32(RX, TX, or eTX) 32(RD or eTX) + 32(RX eTX) 48(RD or eTX) + 48(RX eTX) 48(RD or eTX) + 48(RX eTX) © July 2010 Altera Corporation ...
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... SERDES and DPA block diagram. This diagram shows the interface signals for the transmitter and receiver datapaths. For more information, refer to Transmitter” on page 8–7 © July 2010 Altera Corporation 572-Pin FlipChip FBGA 780-Pin FlipChip FBGA 33(RD or eTX) + 32(RX, TX, or eTX) ...
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... Serial LVDS Clock Phases Center/Corner PLL rx_inclock/tx_inclock LVDS SERDES and DPA Block Diagram tx_out + - LVDS Transmitter rx_in + - DPA Circuitry Retimed Data DIN DPA Clock (DPA_LOAD_EN, DPA_diffioclk, rx_divfwdclk) LVDS Receiver LVDS Clock Domain DPA Clock Domain © July 2010 Altera Corporation ...
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... You can bypass the serializer to support DDR (×2) and SDR (×1) operations to achieve a serialization factor of 2 and 1, respectively. The I/O element (IOE) contains two data output registers that can each operate in either DDR or SDR mode. the serializer bypass path. © July 2010 Altera Corporation (Note 1), (2) IOE supports SDR, DDR, or ...
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... Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II GX Devices (Note 1), (2), (3) IOE supports SDR, DDR, or Serializer 2 IOE Non-Registered Datapath DOUT DIN LVDS Transmitter 3 tx_inclock Center/Corner PLL Transmitter Circuit Parallel Series center/ diffioclk corner PLL LVDS_LOAD_EN Differential Transmitter tx_out + - LVDS Clock Domain txclkout+ txclkout– © July 2010 Altera Corporation ...
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... Arria II GX devices support the following receiver modes to overcome skew between the source-synchronous or reference clock and the received serial data: ■ Non-DPA mode DPA mode ■ ■ Soft clock data recovery (CDR) mode © July 2010 Altera Corporation (Note 1), (2) IOE Synchronizer Bit Slip DOUT DIN DOUT DIN ...
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... DPA circuitry in user mode. The DPA circuitry must be retrained after reset. Arria II GX Device Handbook, Volume 1 Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II GX Devices Figure 8–7 shows the possible phase relationships (Note vco vco Differential Receiver Dn © July 2010 Altera Corporation ...
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... DPA first locks to the incoming data. An optional signal (rx_fifo_reset) is available to the FPGA fabric to reset the synchronizer. Altera recommends using rx_fifo_reset to reset the synchronizer when the DPA signal loss-of-lock condition and the data checker indicates corrupted received data. ...
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... DDR or SDR mode. Arria II GX Device Handbook, Volume 1 Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II GX Devices 321x 3210 Differential Receiver 1 0 xx21 0321 Figure 8–10. You can use © July 2010 Altera Corporation ...
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... Both data realignment and deserializer blocks are clocked by the LVDS_diffioclk clock. When interfacing with non-DPA receivers at data rate above 840 Mbps, you must perform PCB trace compensation to adjust the trace length of each LVDS channel to improve the channel-to-channel skews. © July 2010 Altera Corporation (Note 1), (2), (3) IOE Synchronizer ...
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... Clock Multiplexer 3 (LVDS_LOAD_EN, LVDS_diffioclk, rx_outclk) 8 Serial LVDS Clock Phases Center/Corner PLL rx_inclock Differential Receiver LVDS Receiver + Synchronizer DPA Circuitr Retimed DIN DOUT DIN N Data DPA Cloc (DPA_LO P P AD_EN, DPA_diffioclk rx_divfwdclk LVDS Clock Domain © July 2010 Altera Corporation rx_in ...
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... Figure 8–12: (1) All disabled blocks and signals are grayed out. (2) In SDR and DDR modes, the data width from the IOE is 1 and 2, respectively. (3) The rx_out port has a maximum data width of 10. © July 2010 Altera Corporation (Note 1), (2), (3) IOE Synchronizer ...
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... DOUT DIN 2 diffioclk Clock Multiplexer 3 (LVDS_LOAD_EN, LVDS_diffioclk, 8 Serial LVDS rx_outclk) Clock Phases Center/Corner PLL rx_inclock Differential Receiver LVDS Receiver rx_in + DPA Circuitry Retimed DIN Data DPA Clock 3 (DPA_LOAD_EN, DPA_diffioclk, rx_divfwdclk) LVDS Clock Domain DPA Clock Domain © July 2010 Altera Corporation ...