EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 288

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

10–4
Table 10–2. Fault Injection Register
Automated Single Event Upset Detection
Error Detection Pin Description
Table 10–3. CRC_ERROR Pin Description
Arria II GX Device Handbook, Volume 1
Content
Note to
(1) Bit[20] and Bit[19] cannot both be set to 1, as this is not a valid selection. The error detection circuitry decodes this as no error injection.
CRC_ERROR
Description
Pin Name
Bit
Table
10–2:
Bit[20] Bit[19]
1
Error Type
0
1
0
I/O, output
open-drain
Pin Type
You can only introduce error injection in the first data frame, but you can monitor the
error information at any time. For more information about the JTAG fault injection
register and fault injection register, refer to
Table 10–2
injection.
Arria II GX devices offer on-chip circuitry for automated checking of SEU detection.
Some applications that require the device to operate error-free in high-neutron flux
environments require periodic checks to ensure continued data integrity. The error
detection CRC feature ensures data reliability and is one of the best options for
mitigating SEU.
You can implement the error detection CRC feature with existing circuitry in
Arria II GX devices, eliminating the need for external logic. The CRC_ERROR pin
reports a soft error when configuration CRAM data is corrupted; you must decide
whether to reconfigure the device or to ignore the error.
The following sections describe the CRC_ERROR pin.
Table 10–3
(1)
1
0
0
Active high signal indicating that the error detection circuit has detected errors in the
configuration CRAM bits. This is an optional pin and is used when the error detection CRC
circuit is enabled. When the error detection CRC circuit is disabled, it is a user I/O pin.
When using the WYSIWYG function, the CRC error output is a dedicated path to the
CRC_ERROR pin.
To use the CRC_ERROR pin, tie this pin to V
depending on the input voltage specification of the system receiving the signal, tie this pin
to a different pull-up voltage.
Error injection type
Single byte error injection
Double-adjacent byte error
injection
No error injection
Bit[20..19]
Error Type
lists how the fault injection register is implemented and describes error
lists the CRC_ERROR pin.
Depicts the byte location
of the injected error in the
first data frame.
Byte Location of the
Description
“Error Detection Registers” on page
Injected Error
Bit[18..8]
CCIO
Chapter 10: SEU Mitigation in Arria II GX Devices
through a 10-k resistor. Alternatively,
© July 2010 Altera Corporation
Depicts the bit location of
the error and corresponds
to the error injection type
selection.
Error Detection Pin Description
Error Byte Value
Bit[7..0]
10–6.