EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 300

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

11–6
Boundary-Scan Description Language Support
Revision History
Table 11–4. Document Revision History
Arria II GX Device Handbook, Volume 1
July 2010
November 2009
February 2009
Date
f
f
The boundary-scan description language (BSDL), a subset of VHDL, provides a
syntax that allows you to describe the features of an IEEE Std. 1149.6 BST-capable
device that can be tested. You can test software development systems, then use the
BSDL files for test generation, analysis, and failure diagnostics.
For more information about BSDL files for IEEE Std. 1149.6-compliant Arria II GX
devices, refer to the
You can also generate BSDL files (pre-configuration and post-configuration) for
IEEE Std. 1149.6-compliant Arria II GX devices with the Quartus
version 9.1 and later. For the procedure to generate BSDL files using the Quartus II
software, refer to
Table 11–4
Version
3.0
2.0
1.0
lists the revision history for this chapter.
Updated for Arria II GX v10.0 release:
■
■
Updated for Arria II GX v9.1 release:
■
■
■
Initial release.
Updated
Minor text edits.
Updated Table 11–1 and Table 11–2.
Updated “I/O Voltage Support in a JTAG Chain” section.
Minor text edits.
BSDL Files Generation in
IEEE 1149.6 BSDL Files
“BST Operation Control”
Changes Made
section.
QII.
page on the Altera
Boundary-Scan Description Language Support
Chapter 11: JTAG Boundary-Scan Testing
© July 2010 Altera Corporation
®
website.
®
II software