EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 204

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

8–20
Source-Synchronous Timing Budget
Differential Data Orientation
Differential I/O Bit Position
Arria II GX Device Handbook, Volume 1
This section describes the timing budget, waveforms, and specifications for
source-synchronous signaling in the Arria II GX devices. Timing analysis for the
differential block is different from traditional synchronous timing analysis techniques.
Therefore, it is important to understand how to analyze timing for high-speed
differential signals. This section defines the source-synchronous differential data
orientation timing parameters, timing budget definitions, and how to use these timing
parameters to determine your design’s maximum performance.
There is a set relationship between an external clock and the incoming data. For
operation at 1 Gbps and a serialization factor of 10, the external clock is multiplied
by 10. You can set the phase-alignment in the PLL to coincide with the sampling
window of each data bit. The data is sampled on the falling edge of the multiplied
clock.
Figure 8–18
Figure 8–18. Bit Orientation
Data synchronization is necessary for successful data transmission at high
frequencies.
figures are based on the following:
■
■
■
For other serialization factors, use the Quartus II software tools and find the bit
position in the word. The bit positions after deserialization are listed in
Serialization factor equals clock multiplication factor
Edge alignment is selected for phase alignment
Implemented in hard SERDES
inclock/outclock
shows the data bit orientation of the ×10 mode.
Figure 8–19
data in
shows data bit orientation for a channel operation. These
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II GX Devices
MSB
9
8
7
6
10 LVDS Bits
5
4
3
Source-Synchronous Timing Budget
© July 2010 Altera Corporation
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1
LSB
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Table
8–6.