EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet
EP2AGX45DF29I5N
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EP2AGX45DF29I5N Summary of contents
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... Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat. & Tm. Off. and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective holders as described at www ...
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... EP2AGX125 ES Figure 1 shows the reference clock pre-divider CMU PLL Lock Detect /M Charge Pump + PFD VCO /L Loop Filter chapter in volume 2 of the Arria II Planned Fix EP2AGX125 production devices EP2AGX125 production devices None Software fix pll_locked CMU0 High-Speed Clock February 2011 Altera Corporation ...
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... PLL lock status signal. Figure 3. Instantiating and Connecting the pll_locked_soft_logic Module top_cal_blk_clk top_pll_inclk xcvr_reset_logic xcvr_async_reset xcvr_async_reset system_clk clk pll_locked inst3 f Click pll_locked_soft_logic February 2011 Altera Corporation Figure serdes_io cal_blk_clk pll_inclk pll_powerdown[0..0] tx_datain[39..0] pll_powerdown tx_datain[39..0] tx_digitalreset tx_digitalreset[0..0] inst pll_locked_soft_logic clk ...
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... The transceiver channels configured in PCIe mode are NOT affected by this issue. Solution This issue is fixed in the Quartus II software versions 10.1 and later. Altera recommends upgrading to the latest Quartus II software and recompiling your design. For complete details of the solution, refer to the Additionally, software patches are available for the Quartus II software versions 9 ...
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... Transceiver CDR f If you need additional support, file a service request at Altera's mysupport. External Memory Interface DLL Frequency Range Update The Arria II GX DLL range has been updated in the Quartus II software version 10.0 SP1 and later ...
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... IP block. For correct operation with the hard IP block, logical channel 0 must be placed in physical channel 0. This issue is fixed in the Quartus II software version 10.0; however, Altera recommends upgrading to the Quartus II software version 10.0 SP1. If you have already designed or fabricated your boards using the incorrect mapping, file a service ...
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... Workaround A soft IP solution for this issue is available by contacting Altera. Error Detection CRC Feature The Error Detection CRC feature is typically used to detect single event upsets (SEU). When enabled, the Error Detection CRC feature may cause the memory logic array block (MLAB) RAM to operate incorrectly in Arria devices. Only write operations in the MLAB RAM blocks are affected ...
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... In correct operation, the Arria II GX device should revert back to the factory configuration image after a configuration error is detected with the invalid configuration image. Errata Sheet for Arria II GX Devices M9K RAM Block Lock-Up February 2011 Altera Corporation ...
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... Added “High I/O Pin Leakage Current” and “XAUI State Machine Failure—Channel 0 Shifted August 2009 2.0 by One Cycle” sections. June 2009 1.0 Initial release. February 2011 Altera Corporation ® Technical Support at www.altera.com/support Changes “Transmitter PLL Lock (pll_locked) Status Signal” Page 9 for assistance ...
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... Page 10 Errata Sheet for Arria II GX Devices Document Revision History February 2011 Altera Corporation ...