EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 286

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

10–2
Configuration Error Detection
User Mode Error Detection
Arria II GX Device Handbook, Volume 1
In configuration mode, a frame-based CRC is stored in the configuration data and
contains the CRC value for each data frame.
During configuration, the Arria II GX device calculates the CRC value based on the
frame of data that is received and compares it against the frame CRC value in the data
stream. Configuration continues until either the device detects an error or
configuration is complete.
In Arria II GX devices, the CRC value is calculated during the configuration stage. A
parallel CRC engine generates 16 CRC check bits per frame and then stores them into
the configuration random access memory (CRAM). The CRAM chain used for storing
CRC check bits is 16-bits wide; its length is equal to the number of frames in the
device.
Arria II GX devices have built-in error detection circuitry to detect data corruption by
soft errors in the CRAM cells. This feature allows all CRAM contents to be read and
verified to match a configuration-computed CRC value. Soft errors are changes in a
CRAM’s bit state due to an ionizing particle.
The error detection capability continuously computes the CRC of the configured
CRAM bits and compares it with the pre-calculated CRC. If the CRCs match, there is
no error in the current configuration CRAM bits. The process of error detection
continues until the device is reset by setting nCONFIG low.
When the device transitions into user mode, the error detection process is enabled if
you enabled the CRC error detection option in the Quartus II software.
A single 16-bit CRC calculation is done on a per-frame basis. After it has finished the
CRC calculation for a frame, the resulting 16-bit signature is hex 0000, if there are no
detected CRAM bit errors in a frame by the error detection circuitry and the output
signal CRC_ERROR is 0. If a CRAM bit error is detected by the circuitry in a frame in
the device, the resulting signature is non-zero. This causes the CRC engine to start
searching the error bit location.
The error detection logic in Arria II GX devices calculates CRC check bits for each
frame and pulls the CRC_ERROR pin high when it detects bit errors in the chip. Within
a frame, it can detect all single-bit, double-bit, and three-bit errors. The probability of
more than three CRAM bits being flipped by a single event upset (SEU) is very low. In
general, the probability of detection for all error patterns is 99.998%.
The CRC engine reports the bit location and determines the type of error for all
single-bit errors and over 99.641% of double-adjacent errors. The probability of other
error patterns is very low and a report of the location of bit flips is not guaranteed by
the CRC engine.
You can also read out the error bit location through the JTAG and the core interface.
You must shift these bits out from the error message register through either the JTAG
instruction, SHIFT_EDERROR_REG, or the core interface before the CRC detects the
next error in another frame. The CRC circuit continues to run, and if an error is
detected, you must decide whether to complete a reconfiguration or to ignore the
CRC error.
Chapter 10: SEU Mitigation in Arria II GX Devices
© July 2010 Altera Corporation
Configuration Error Detection