EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 273

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices
Dedicated Remote System Upgrade Circuitry
Remote System Upgrade State Machine
© July 2010
Altera Corporation
1
Table 9–16. Remote System Upgrade Status Register Contents (Part 2 of 2)
The remote system upgrade control and update registers have identical bit
definitions, but serve different roles (refer to
registers can only be updated when the device is loaded with a factory configuration
image, the update register writes are controlled by the user logic; the control register
writes are controlled by the remote system upgrade state machine.
In factory configurations, the user logic sends the AnF bit (set high), page address, and
watchdog timer settings for the next application configuration bit to the update
register. When the logic array configuration reset (RU_nCONFIG) goes low, the remote
system upgrade state machine updates the control register with the contents of the
update register and starts system reconfiguration from the new application page.
To ensure successful reconfiguration between the pages, assert the RU_nCONFIG
signal for a minimum of 250 ns. This is equivalent to strobing the reconfig input of
the ALTREMOTE_UPDATE megafunction high for a minimum of 250 ns.
If there is an error or reconfiguration trigger condition, the remote system upgrade
state machine directs the system to load a factory or application configuration (page
zero or page one, based on the mode and error condition) by setting the control
register accordingly.
event occurs for all possible error or trigger conditions.
The remote system upgrade status register is updated by the dedicated error
monitoring circuitry after an error condition but before the factory configuration is
loaded.
Table 9–17. Control Register Contents after an Error or Reconfiguration Trigger Condition
Capture operations during factory configuration access the contents of the update
register. This feature is used by the user logic to verify that the page address and
watchdog timer settings were written correctly. Read operations in application
configurations access the contents of the control register. This information is used by
the user logic in the application configuration.
Wd
Note to
(1) Logic array reconfiguration forces the system to load the application configuration data into the Arria II GX device.
nCONFIG reset
nSTATUS error
CORE triggered reconfiguration
CRC error
Wd time out
Status Register Bit
This occurs after the factory configuration specifies the appropriate application configuration page address by
updating the update register.
Reconfiguration Error/Trigger
Table
9–16:
Table 9–17
Watchdog timer caused reconfiguration
lists the contents of the control register after such an
Definition
Control Register Setting Remote Update
Figure 9–26 on page
Update register
All bits are 0
All bits are 0
All bits are 0
All bits are 0
Arria II GX Device Handbook, Volume 1
9–51). While both
POR Reset Value
1 bit '0'
9–53