EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 181

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 7: External Memory Interfaces in Arria II GX Devices
Arria II GX External Memory Interface Features
Figure 7–15. Avoiding Glitch on a Non-Consecutive Read Burst Waveform
I/O Element Registers
© July 2010 Altera Corporation
Postamble Enable
dqsenable
DQS
DQS Postamble Circuitry
For external memory interfaces that use a bidirectional read strobe such as in DDR3,
DDR2, and DDR SDRAM, the DQS signal is low before going to or coming from a
high-impedance state. The state in which DQS is low, just after a high-impedance
state, is called the preamble; the state in which DQS is low, just before it returns to a
high-impedance state, is called the postamble. There are preamble and postamble
specifications for both read and write operations in DDR3, DDR2, and DDR SDRAM.
The DQS postamble circuitry ensures that data is not lost if there is noise on the DQS
line at the end of a read postamble time.
Arria II GX devices have dedicated postamble registers that can be controlled to
ground the shifted DQS signal used to clock the DQ input registers at the end of a
read operation. This ensures that any glitches on the DQS input signals at the end of
the read postamble time do not affect the DQ IOE registers.
There is an AND gate after the postamble register outputs that is used to avoid
postamble glitches from a previous read burst on a non-consecutive read burst. This
scheme allows a half-a-clock cycle latency for dqsenable assertion and zero latency
for dqsenable de-assertion, as shown in
IOE registers are expanded to allow source-synchronous systems to have faster
register-to-register transfers and resynchronization. Both top, bottom, and right IOEs
have the same capability. Right IOEs have extra features to support LVDS data
transfer.
Figure 7–16
consists of DDR input registers and resynchronization registers. You can bypass each
block of the input path.
shows the registers available in the Arria II GX input path. The input path
Figure
Postamble
7–15.
Postamble glitch
Arria II GX Device Handbook, Volume 1
Preamble
Delayed by
1/2T logic
7–23