EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 21

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: Arria II GX Device Family Overview
Arria II GX Device Architecture
PCIe Hard IP Block
Logic Array Block and Adaptive Logic Modules
Embedded Memory Blocks
© July 2010 Altera Corporation
Every Arria II GX device includes an integrated hard-IP block which implements
PCIe PHY/MAC, data link, and transaction layers. This PCIe hard IP block is highly
configurable to meet the requirements of the majority of PCIe applications. PCIe hard
IP makes implementing a PCIe Gen1 solution in your Arria II GX design simple and
easy.
You can instantiate PCIe hard IP block using the PCI Compiler MegaWizard
Manager, similar to soft IP functions, but does not consume core FPGA resources or
require placement, routing, and timing analysis to ensure correct operation of the
core. The Arria II GX PCIe hard IP block includes support for:
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×1, ×4, and ×8 lane configurations
Root port and endpoint configurations
512-byte payload
Compliant to PCIe 1.1 at 2.5 Gbps
Logic array blocks (LABs) consists of 10 ALMs, carry chains, shared arithmetic
chains, LAB control signals, local interconnect, and register chain connection lines
ALMs expand the traditional four-input LUT architecture to eight-inputs,
increasing performance by reducing logic elements (LEs), logic levels, and
associated routing
LABs have a derivative called MLAB, which adds SRAM-memory capability to
the LAB
MLAB and LAB blocks always coexist as pairs, allowing up to 50% of the logic
(LABs) to be traded for memory (MLABs)
M9K embedded memory blocks provide up to 8,550 Kbits of on-chip memory
capable of up to 390-MHz performance. The embedded memory structure consists
of columns of M9K memory blocks that you can configure as RAM, FIFO buffers,
and ROM.
Optimized for applications such as high-throughput packet processing,
high-definition (HD) line buffers for video processing functions, and embedded
processor program and data storage.
The Quartus
instantiating memory using a dedicated megafunction wizard or by inferring
memory directly from VHDL or Verilog source code.
®
II software allows you to take advantage of M9K memory blocks by
Arria II GX Device Handbook, Volume 1
TM
Plug-In
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