EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 242

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

9–22
Passive Serial Configuration
PS Configuration Using an External Host
Arria II GX Device Handbook, Volume 1
f
f
1
For more information about SRunner, refer to
for EPCS Programming
For more information about programming serial configuration devices, refer to the
Serial Configuration Devices (EPCS1, EPCS4, EPCS16, EPCS64, and EPCS128) Data Sheet
chapter in volume 2 of the Configuration Handbook.
You can program PS configuration of Arria II GX devices using an intelligent host,
such as a MAX II device or microprocessor with flash memory, or a download cable.
In the PS scheme, an external host (a MAX II device, embedded processor, or host PC)
controls configuration. Configuration data is clocked into the target Arria II GX device
using the DATA0 pin at each rising edge of DCLK.
The Arria II GX decompression and design security features are available when
configuring your Arria II GX device using PS mode.
In this configuration scheme, you can use a MAX II device as an intelligent host that
controls the transfer of configuration data from a storage device, such as flash
memory, to the target Arria II GX device. You can store configuration data in .rbf,
.hex, or .ttf format.
Figure 9–10
device and a MAX II device for single device configuration.
Figure 9–10. Single Device PS Configuration Using an External Host
Notes to
(1) Connect the resistor to a supply that provides an acceptable input signal for the Arria II GX device. V
(2) The nCEO pin can be left unconnected or used as a user I/O pin when it does not feed the nCE pin of the other device.
(3) The MSEL pin settings vary for different configuration voltage standards and POR delays. To connect MSEL[3..0],
enough to meet the V
up the configuration system's I/Os with V
refer to
Figure
Table 9–2 on page
shows the configuration interface connections between an Arria II GX
9–10:
(MAX II Device or
Microprocessor)
Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices
External Host
ADDR
IH
Memory
specification of the I/O on the device and the external host. Altera recommends that you power
DATA[0]
and the source code on the
9–7.
CCIO
for I/O bank 3C.
10 k Ω
V
CCIO(1)
10 k Ω
V
AN 418: SRunner: An Embedded Solution
CCIO (1)
GND
Altera
CONF_DONE
nSTATUS
nCE
DATA[0]
nCONFIG
DCLK
Arria II GX Device
website.
© July 2010 Altera Corporation
MSEL[3..0]
Passive Serial Configuration
nCEO
N.C.
(3)
CCIO
(2)
must be high