EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 55

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 3: Memory Blocks in Arria II GX Devices
Clocking Modes
Clocking Modes
Independent Clock Mode
Input and Output Clock Mode
© November 2009
1
Altera Corporation
Arria II GX memory blocks support the following clocking modes:
■
■
■
■
Violating the setup or hold time on the memory block address registers could corrupt
the memory contents. This applies to both read and write operations.
Table 3–6
Table 3–6. Arria II GX Memory Clock Modes
Arria II GX memory blocks can implement independent clock mode for true dual-port
memories. In this mode, a separate clock is available for each port (A and B). Clock A
controls all registers on the port A side, while clock B controls all registers on the
port B side. Each port also supports independent clock enables for port A and port B
registers. Asynchronous clears are supported only for output latches and output
registers on both ports.
Arria II GX memory blocks can implement input and output clock mode for true and
simple dual-port memories. In this mode, an input clock controls all registers related
to the data input to the memory block including data, address, byte enables, read
enables, and write enables. An output clock controls the data output registers.
Asynchronous clears are available on output latches and output registers only.
Independent
Input and output
Read and write
Single clock
Clocking Mode
Independent
Input and output
Read and write
Single clock
lists the clocking mode versus memory mode support matrix.
Dual-Port
Mode
True
v
v
v
—
Dual-Port
Simple
Mode
v
v
v
—
Single-Port
Mode
v
v
—
—
Arria II GX Device Handbook, Volume 1
ROM Mode
v
v
—
v
FIFO Mode
v
v
—
—
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