EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 291

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 10: SEU Mitigation in Arria II GX Devices
Error Detection Timing
Table 10–5. Error Detection Registers (Part 2 of 2)
Error Detection Timing
Table 10–6. Minimum and Maximum Error Detection Frequencies
© July 2010
JTAG Update Register
User Update Register
JTAG Shift Register
User Shift Register
JTAG Fault Injection
Register
Fault Injection Register The content of the JTAG fault injection register is loaded into this 21-bit register when it is
Device Type
Arria II GX
Register
Altera Corporation
Error Detection
100 MHz / 2
When the error detection CRC feature is enabled in the Quartus II software, the device
automatically activates the CRC process upon entering user mode, after
configuration, and after initialization is complete.
If an error is detected within a frame, CRC_ERROR is driven high at the end of the
error location search after the error message register is updated. At the end of this
cycle, the CRC_ERROR pin is pulled low for a minimum of 32 clock cycles. If the next
frame contains an error, CRC_ERROR is driven high again after the error message
register is overwritten by the new value. You can start to unload the error message on
each rising edge of the CRC_ERROR pin. Error detection runs until the device is reset.
The error detection circuitry runs off an internal configuration oscillator with a divisor
that sets the maximum frequency.
detection frequencies.
Frequency
This register is automatically updated with the contents of the error message register one cycle
after the 46-bit register content is validated. It includes a clock enable, which must be asserted
prior to being sampled into the JTAG shift register. This requirement ensures that the JTAG Update
Register is not being written into by the contents of the Error Message Register at the same time
that the JTAG shift register is reading its contents.
This register is automatically updated with the contents of the error message register one cycle
after the 46-bit register content is validated. It includes a clock enable, which must be asserted
prior to being sampled into the user shift register. This requirement ensures that the user update
register is not being written into by the contents of the error message register at exactly the same
time that the user shift register is reading its contents.
This register is accessible by the JTAG interface and allows the contents of the JTAG update
register to be sampled and read out by JTAG instruction SHIFT_EDERROR_REG.
This register is accessible by the core logic and allows the contents of the user update register to
be sampled and read by user logic.
This 21-bit register is fully controlled by the JTAG instruction EDERROR_INJECT. This register
holds the information of the error injection that you want in the bitstream.
updated.
n
Detection Frequency
Maximum Error
50 MHz
Table 10–6
Description
Minimum Error Detection
lists the minimum and maximum error
Frequency
390 kHz
Arria II GX Device Handbook, Volume 1
1, 2, 3, 4, 5, 6, 7, 8
Valid Divisors (n)
10–7