EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 254

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

9–34
Jam STAPL
Device Configuration Pins
Table 9–10. Arria II GX Configuration Pin Summary (Part 1 of 2)
Arria II GX Device Handbook, Volume 1
TDI
TMS
TCK
Description
f
Figure 9–18
microprocessor.
Figure 9–18. JTAG Configuration of a Single Device Using a Microprocessor
Notes to
(1) Connect the pull-up resistor to a supply that provides an acceptable input signal for all Arria II GX devices in the chain.
(2) Connect the nCONFIG and MSEL[3..0] pins to support a non-JTAG configuration scheme. If you use only the
(3) You must connect nCE to GND or drive it low for successful JTAG configuration.
(4) To drive the JTAG pins, the microprocessor must use the same I/O standard as V
Jam standard test and programming language (STAPL), JEDEC standard JESD-71, is a
standard file format for in-system programmability (ISP) purposes. Jam STAPL
supports programming or configuration of programmable devices and testing of
electronic systems, using the IEEE 1149.1 JTAG interface. It is a freely licensed open
standard.
The Jam Player provides an interface for manipulating the IEEE Std. 1149.1 JTAG TAP
state machine.
For more information about JTAG and Jam STAPL in embedded environments, refer
to
download the jam player, visit the
Table 9–10
configuration-related pins on the Arria II GX devices.
configuration pins and their power supply.
AN 425: Using Command-Line Jam STAPL Solution for Device
The V
I/O on the device.
JTAG configuration, connect nCONFIG to the V
MSEL[3..0] to GND. Pull DCLK either high or low, whichever is convenient on your board.
Figure
CCIO
power supply of the bank in which the pin resides must be high enough to meet the V
through
shows a JTAG configuration of an Arria II GX device using a
9–18:
Input/Output
Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices
Input
Input
Input
Microprocessor
Table 9–13
ADDR
Memory
DATA
describe the connections and functionality of all the
Dedicated
Yes
Yes
Yes
Altera
CCIO
power supply of the bank in which the pin resides and
website.
TDI (4)
TCK (4)
TMS (4)
TDO (4)
Arria II GX Device
CONF_DONE
Powered By
MSEL[3..0]
nSTATUS
nCONFIG
(3) nCE
V
V
V
DCLK
nCEO
CCIO
CCIO
CCIO
Table 9–10
V CCIO (1)
(2)
(2)
(2)
N.C.
GND
10 kΩ
CCIO
Programming. To
© July 2010 Altera Corporation
V CCIO (1)
.
lists the Arria II GX
Configuration Mode
10 kΩ
Device Configuration Pins
IH
JTAG
JTAG
JTAG
specification of the