EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 234

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

9–14
Table 9–5. FPP Timing Parameters for Arria II GX Devices with the Decompression or Design Security Features Enabled
Active Serial Configuration (Serial Configuration Devices)
Arria II GX Device Handbook, Volume 1
t
t
t
t
t
t
t
t
t
t
t
t
f
t
t
t
t
t
t
Notes to
(1) Use these timing parameters when the decompression and design security features are used.
(2) This value is obtainable if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width.
(3) The minimum and maximum numbers apply only if you choose the internal oscillator as the clock source for initializing the device.
(Note
Symbol
CF2CD
CF2ST0
CFG
STATUS
CF2ST1
CF2CK
ST2CK
DSU
DH
CH
CL
CLK
MAX
DATA
R
CD2UM
CD2CU
CD2UMC
1)—Preliminary
Table
nCONFIG low to CONF_DONE low
nCONFIG low to nSTATUS low
nCONFIG low pulse width
nSTATUS low pulse width
nCONFIG high to nSTATUS high
nCONFIG high to first rising edge on DCLK
nSTATUS high to first rising edge of DCLK
Data setup time before rising edge on DCLK
Data hold time after rising edge on DCLK
DCLK high time
DCLK low time
DCLK period
DCLK frequency
Data rate
Input rise time
Input fall time
CONF_DONE high to user mode
CONF_DONE high to CLKUSR enabled
CONF_DONE high to user mode with CLKUSR option on
f
9–5:
Table 9–5
when the decompression and/or design security features are enabled.
For more information about setting device configuration options or creating
configuration files, refer to the
Formats
In the AS configuration scheme, Arria II GX devices are configured using a serial
configuration device. These configuration devices are low-cost devices with
non-volatile memory that feature a simple four-pin interface and a small form factor.
These features make serial configuration devices an ideal low-cost configuration
solution.
chapters in volume 2 of the Configuration Handbook.
lists the timing parameters for Arria II GX devices for FPP configuration
Parameter
Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices
(3)
Device Configuration Options
t
4 × maximum
CD2CU
DCLK period
Minimum
Active Serial Configuration (Serial Configuration Devices)
CLKUSR
period)
+ (8532 ×
500
3.2
3.2
—
—
10
—
24
—
—
—
—
55
2
2
4
8
and
Maximum
500
500
© July 2010 Altera Corporation
800
800
125
250
150
—
—
—
—
—
—
—
—
40
40
—
—
Configuration File
(2)
(2)
Mbps
Units
MHz
ns
ns
s
s
s
s
s
ns
ns
ns
ns
ns
ns
ns
—
—
s