EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 102

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

5–10
Clock Enable Signals
Figure 5–7. clkena Implementation
Notes to
(1) The R1 and R2 bypass paths are not available for PLL external clock outputs.
(2) The select line is statically controlled by a bit setting in the configuration file (.sof or .pof).
Arria II GX Device Handbook, Volume 1
Figure
5–7:
select multiplexer
output of clock
Figure 5–6. Arria II GX External PLL Output Clock Control Block
Notes to
(1) This clock select signal can only be set through a configuration file (.sof or .pof) and cannot be dynamically controlled
(2) The clock control block feeds a multiplexer in the PLL<#>_CLKOUT pin’s IOE. The PLL<#>_CLKOUT pin is a dual-
Figure 5–7
implemented in Arria II GX devices.
clkena
during user mode operation.
purpose pin. Therefore, this multiplexer selects either an internal signal or the output of the clock control block.
Figure
shows how the clock enable/disable circuit of the clock control block is
D
(1)
5–6:
R1
Q
D
R2
IOE
(1)
Internal
Q
Logic
(2)
PLL<#>_CLKOUT pin
Outputs and m Counter
PLL Counter
Enable/
Disable
8
(2)
Chapter 5: Clock Networks and PLLs in Arria II GX Devices
Internal
Static Clock
Select (1)
Logic
Static Clock Select
GCLK/
RCLK/
PLL_<#>_CLKOUT (1)
Clock Networks in Arria II GX Devices
(1)
© July 2010 Altera Corporation