EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 282

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

9–62
Table 9–21. Allowed Configuration Modes for Various Security Modes
Arria II GX Device Handbook, Volume 1
Secure in tamper resistant
mode using volatile or
non-volatile key with tamper
protection
Note to
(1) There is no impact to the configuration time required when compared with unencrypted configuration modes except when using FPP with AES
(and/or decompression), which requires DCLK that is 4× the data rate.
Table
Security Mode
9–21:
1
The design security feature is available in all configuration methods except JTAG.
Therefore, you can use the design security feature in FPP mode (when using an
external controller, such as a MAX II device or a microprocessor and flash memory),
or in AS and PS configuration schemes.
Table 9–22
both for volatile key and non-volatile key programming.
Table 9–22. Design Security Configuration Schemes Availability
You can use the design security feature with other configuration features, such as the
compression and remote system upgrade features. When you use compression with
the design security feature, the configuration file is first compressed and then
encrypted using the Quartus II software. During configuration, the Arria II GX device
first decrypts and then decompresses the configuration file.
FPP
AS
PS
JTAG
Notes to
(1) In this mode, the host system must send a DCLK that is 4× the data rate.
(2) JTAG configuration supports only unencrypted configuration file.
Configuration Scheme
(2)
Table
Configuration
lists the configuration schemes that support the design security feature
Encrypted
9–22:
File
Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices
MAX II device or microprocessor and flash memory
Serial configuration device
MAX II device or microprocessor and flash memory
Download cable
MAX II device or microprocessor and flash memory
Download cable
■
■
■
■
PS with AES (and/or with decompression)
FPP with AES (and/or with decompression)
Remote update AS with AES (and/or with decompression)
AS (and/or with decompression)
Configuration Method
(Note 1)
Allowed Configuration Modes
(Part 2 of 2)
© July 2010 Altera Corporation
Design Security
Security
Design
v
v
v
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(1)