EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 195

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II GX Devices
Differential Receiver
Synchronizer
Data Realignment Block (Bit Slip)
© July 2010
Altera Corporation
The synchronizer is a 1-bit wide and 6-bit deep FIFO buffer that compensates for the
phase difference between DPA_diffioclk and the high-speed clock
(LVDS_diffioclk) produced by the center/corner PLL. Because every DPA channel
might have a different phase selected to sample the data, you need the FIFO buffer to
synchronize the data to the high-speed LVDS clock domain. The synchronizer can
only compensate for phase differences, not frequency differences between the data
and the input reference clock of the receiver, and is automatically reset when the DPA
first locks to the incoming data.
An optional signal (rx_fifo_reset) is available to the FPGA fabric to reset the
synchronizer. Altera recommends using rx_fifo_reset to reset the synchronizer
when the DPA signal is in a loss-of-lock condition and the data checker indicates
corrupted received data.
Skew in the transmitted data along with skew added by the link causes
channel-to-channel skew on the received serial data streams. If you enabled DPA, the
received data is captured with different clock phases on each channel. This might
cause the received data to be misaligned from channel to channel. To compensate for
this channel-to-channel skew and establish the correct received word boundary at
each channel, each receiver channel has a dedicated data realignment circuit that
realigns the data by inserting bit latencies into the serial stream.
An optional signal (rx_channel_data_align) controls the bit insertion of each
receiver independently controlled from the internal logic. The data slips one bit on the
rising edge of rx_channel_data_align. The following are requirements for the
rx_channel_data_align signal:
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■
■
■
■
An edge-triggered signal
The minimum pulse width is one period of the parallel clock in the logic array
The minimum low time between pulses is one period of the parallel clock
Holding rx_channel_data_align does not result in extra slips
Valid data is available two parallel clock cycles after the rising edge of the
rx_channel_data_align signal
Arria II GX Device Handbook, Volume 1
8–11