ADF4193BCPZ Analog Devices Inc, ADF4193BCPZ Datasheet - Page 25

• Manufacturer Part Number: ADF4193BCPZ
• Description: IC PLL FREQ SYNTHESIZER 32LFCSP
• Manufacturer: Analog Devices Inc
• Type: Clock/Frequency Synthesizer (RF)r

Specifications of ADF4193BCPZ

• Pll: Yes
• Input: CMOS
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:1
• Differential - Input:output: Yes/No
• Frequency - Max: 3.5GHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 2.7 V ~ 3.3 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-LFCSP
• Frequency-max: 3.5GHz
• Pll Type: Frequency Synthesis
• Frequency: 3.5GHz
• Supply Current: 24mA
• Supply Voltage Range: 2.7V To 3.3V
• Digital Ic Case Style: LFCSP
• No. Of Pins: 32
• Operating Temperature Range: -40°C To +85°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADF4193EBZ2 - BOARD EVALUATION EB2 FOR ADF4193EVAL-ADF4193EBZ1 - BOARD EVALUATION EB1 FOR ADF4193
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

APPLICATIONS
LOCAL OSCILLATOR FOR A GSM BASE STATION
Figure 36 shows the ADF4193 being used with a VCO to
produce the LO for a GSM1800 base station. For GSM, the
REF
main requirement is that the slew rate is at least 300 V/μs.
The 5 dBm, 104 MHz input sine wave shown satisfies this
requirement.
Recommended parameters for the various GSM/PCS/DCS
synthesizers are given in Table 9.
Table 9. Recommended Setup Parameters
Parameter
Loop BW
PFD (MHz)
MOD
Dither
Prescaler
ICP Timer
SW1, SW2,
SW3 Timers
VCO K
Loop BW and PFD Frequency
A 60 kHz loop BW is narrow enough to attenuate the PLL phase
noise and spurs to the required level for a Tx low. A 40 kHz BW
is necessary to meet the GSM900 Rx synthesizer’s particularly
tough phase noise and spur requirements at ±800 kHz offsets.
To get the lowest spur levels at ±800 kHz offsets for Rx, the Σ-Δ
modulator should be run at the highest oversampling rate
possible. Therefore, for GSM900 Rx, a 26 MHz PFD frequency
is chosen and MOD = 130 is required for 200 kHz steps.
Because this value of MOD is divisible by two, certain FRAC
channels have a 100 kHz fractional spur. This is attenuated by
the 40 kHz loop filter and therefore is not a concern. However,
the 60 kHz loop filter recommended for Tx has a closed-loop
response that peaks close to 100 kHz. Therefore, a 13 MHz PFD
with MOD = 65, which avoids the 100 kHz spur, is the best
choice for a Tx synthesizer.
Dither
Dither off should be selected for the lowest rms phase error.
Prescaler
The 8/9 prescaler should be selected for the PCS and DCS
bands. The 4/5 prescaler allows an N divider range low enough
to cover the GSM900 Tx and Rx bands with either a 13 MHz or
26 MHz PFD frequency.
IN
V
signal can be any integer multiple of 13 MHz, but the
Tx
60 kHz
13
65
Off
4/5
28
35
18 MHz/V
GSM900
Rx
40 kHz
26
130
Off
4/5
78
85
18 MHz/V
Tx
60 kHz
13
65
Off
8/9
28
35
38 MHz/V
DCS1800/PCS1900
Rx
40 kHz
13
65
Off
8/9
38
45
38 MHz/V
Rev. C | Page 25 of 28
Timer Values for Tx
To comply with the GSM spectrum due to switching require-
ments, the Tx synthesizer should not switch frequency until the
PA output power has ramped down by at least 50 dB. If it takes
10 μs to ramp down to this level, then only the last 20 μs of the
30 μs guard period is available for the Tx synthesizer to lock to
final frequency and phase.
In fast lock mode, the Tx loop BW is widened by a factor-of-8
to 480 kHz, and therefore, the PLL achieves frequency lock for
a jump across the entire band in <6 μs. After this, the PA power
can start to ramp up again, and the loop BW can be restored to
the final value. With the ICP timer = 28, the charge pump current
reduction begins at ~8.6 μs. When SW1, SW2, and SW3 timers =
35, the current reaches its final value before the loop filter
switches open at ~10.8 μs.
With these timer values, the phase disturbance created when
the bandwidth is reduced settles back to its final value by 20 μs,
in time for the start of the active part of the GSM burst. If faster
phase settling is desired with the 60 kHz BW setting, then the timer
values can be reduced further but should not be brought less than
the 6 μs it takes to achieve frequency lock in wide BW mode.
Timer Values for Rx
The 40 kHz Rx loop BW is increased by a factor-of-8 to
approximately 320 kHz during fast lock. With the Rx timer
values shown, the BW is reduced after ~12 μs, which allows
sufficient time for the phase disturbance to settle back before
the start of the active part of the Rx time slot at 30 μs. As in the
Tx case, faster Rx settling can be achieved by reducing these
timer values, their lower limit being determined by the time it
takes to achieve frequency lock in wide BW mode. In addition,
the PCS and DCS Rx synthesizers have relaxed 800 kHz blocker
specifications and thus can tolerate a wider loop BW, which
allows correspondingly faster settling.
VCO K
In general, the VCO gain, K
minimize the reference and integer boundary spur levels that arise
due to feedthrough mechanisms. When deciding on the optimum
VCO K
band, centered on the available tuning range. With V
to 5.5 V ± 100 mV, the tuning range available is 2.8 V.
Loop Filter Components
It is important for good settling performance that capacitors
with low dielectric absorption are used in the loop filter.
Ceramic NPO COG capacitors are a good choice for this
application. A 2% tolerance is recommended for loop filter
capacitors and 1% for resistors. A 10% tolerance is adequate
for the inductor, L1.
V
V
, a good choice is to allow 2 V to tune across the desired
V
, should be set as low as possible to
ADF4193
P
3 regulated