ADF4193BCPZ Analog Devices Inc, ADF4193BCPZ Datasheet - Page 15

• Manufacturer Part Number: ADF4193BCPZ
• Description: IC PLL FREQ SYNTHESIZER 32LFCSP
• Manufacturer: Analog Devices Inc
• Type: Clock/Frequency Synthesizer (RF)r

Specifications of ADF4193BCPZ

• Pll: Yes
• Input: CMOS
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:1
• Differential - Input:output: Yes/No
• Frequency - Max: 3.5GHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 2.7 V ~ 3.3 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-LFCSP
• Frequency-max: 3.5GHz
• Pll Type: Frequency Synthesis
• Frequency: 3.5GHz
• Supply Current: 24mA
• Supply Voltage Range: 2.7V To 3.3V
• Digital Ic Case Style: LFCSP
• No. Of Pins: 32
• Operating Temperature Range: -40°C To +85°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADF4193EBZ2 - BOARD EVALUATION EB2 FOR ADF4193EVAL-ADF4193EBZ1 - BOARD EVALUATION EB1 FOR ADF4193
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

FRAC/INT REGISTER (R0)
R0, the FRAC/INT register, is used to program the synthesizer
output frequency. On the next PFD cycle following a write to
R0, the N divider section is updated with the new INT and
FRAC values. At the same time, the PLL automatically enters
fast lock mode and the charge pump current is increased to its
maximum value and stays at this value until the ICP timeout
counter times out, and switches SW1, SW2, and SW3 closed
and remains closed until the SW1, SW2, and SW3 timeout
counters time out.
Once all registers are programmed during the initialization
sequence (see Table 8), all that is required thereafter to program
a new channel is a write to R0. However, as described in the
Programming section, it can also be desirable to program R1
and R2 register settings on a channel-by-channel basis. These
settings are double buffered by the write to R0. This means
that while the data is loaded through the serial interface on the
respective R1 and R2 write cycles, the synthesizer is not updated
with their data until the next write to Register R0.
DB23
0
DB22
N8
DB21
N7
N8
0
.
.
.
1
DB20
8-BIT RF INT VALUE
N6
DB19
N5
N7
0
.
.
.
1
DB18
N4
N6
0
.
.
.
1
DB17
N3
DB16
N5
1
.
.
.
1
N2
F12
0
0
0
0
.
.
.
1
1
1
1
DB15
N1
N4
1
.
.
.
1
DB14
F12
F11
0
0
0
0
.
.
.
1
1
1
1
Figure 29. FRAC/INT Register (R0)
N3
0
.
.
.
1
DB13
F11
Rev. C | Page 15 of 28
F10
0
0
0
0
.
.
.
1
1
1
1
DB12
F10
N2
1
.
.
.
1
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
DB11
F9
Control Bits
The three LSBs, Control Bit C3, Control Bit C2, and Control Bit C1,
should be set to 0, 0, 0, respectively, to select R0, the FRAC/INT
register.
Reserved Bit
Bit DB23 is reserved and must be set to 0.
8-Bit INT Value
These eight bits set the INT value, which determines the integer
part of the feedback division factor. All integer values from 26
to 255 are allowed. See the Worked Example section.
12-Bit FRAC Value
The 12 FRAC bits set the numerator of the fraction that is input
to the Σ-Δ modulator. This, along with INT, specifies the new
frequency channel that the synthesizer locks to, as shown in the
Worked Example section. FRAC values from 0 to MOD − 1
cover channels over a frequency range equal to the PFD reference
frequency.
N1
0
.
.
.
1
DB10
F8
12-BIT RF FRAC VALUE
F3
0
0
0
0
.
.
.
1
1
1
1
DB9
F7
INTEGER VALUE (INT)
26
.
.
.
255
DB8
F6
F2
0
0
1
1
.
.
.
0
0
1
1
DB7
F5
F1
0
1
0
1
.
.
.
0
1
0
1
DB6
F4
DB5
0 = < FRAC < MOD
FRACTIONAL VALUE (FRAC)
0
1
2
3
.
.
.
4092
4093
4094
4095
F3
DB4
F2
DB3
F1
C3 (0)
DB2
ADF4193
CONTROL
C2 (0)
BITS
DB1
C1 (0)
DB0