ADF4193BCPZ Analog Devices Inc, ADF4193BCPZ Datasheet

IC PLL FREQ SYNTHESIZER 32LFCSP

ADF4193BCPZ

Manufacturer Part Number
ADF4193BCPZ
Description
IC PLL FREQ SYNTHESIZER 32LFCSP
Manufacturer
Analog Devices Inc
Type
Clock/Frequency Synthesizer (RF)r
Datasheet

Specifications of ADF4193BCPZ

Pll
Yes
Input
CMOS
Output
Clock
Number Of Circuits
1
Ratio - Input:output
2:1
Differential - Input:output
Yes/No
Frequency - Max
3.5GHz
Divider/multiplier
Yes/Yes
Voltage - Supply
2.7 V ~ 3.3 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
32-LFCSP
Frequency-max
3.5GHz
Pll Type
Frequency Synthesis
Frequency
3.5GHz
Supply Current
24mA
Supply Voltage Range
2.7V To 3.3V
Digital Ic Case Style
LFCSP
No. Of Pins
32
Operating Temperature Range
-40°C To +85°C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
EVAL-ADF4193EBZ2 - BOARD EVALUATION EB2 FOR ADF4193EVAL-ADF4193EBZ1 - BOARD EVALUATION EB1 FOR ADF4193
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ADF4193BCPZ
Quantity:
11 698
Part Number:
ADF4193BCPZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Part Number:
ADF4193BCPZ-RL7
Manufacturer:
AD
Quantity:
800
Part Number:
ADF4193BCPZ-RL7
Manufacturer:
ADI/亚德诺
Quantity:
20 000
FEATURES
New, fast settling, fractional-N PLL architecture
Single PLL replaces ping-pong synthesizers
Frequency hop across GSM band in 5 μs with phase settled
0.5° rms phase error at 2 GHz RF output
Digitally programmable output phase
RF input range up to 3.5 GHz
3-wire serial interface
On-chip, low noise differential amplifier
Phase noise figure of merit: −216 dBc/Hz
Loop filter design possible using ADI SimPLL
Qualified for automotive applications
APPLICATIONS
GSM/EDGE base stations
PHS base stations
Instrumentation and test equipment
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
by 20 μs
MUX
REF
DATA
CLK
OUT
LE
IN
HIGH Z
SDV
A
DD
GND
REGISTER
1
DOUBLER
OUTPUT
DV
24-BIT
DATA
MUX
DD
×2
1
A
GND
DV
DD
FUNCTIONAL BLOCK DIAGRAM
2
R
N
V
DGND
2
DD
DIV
DIV
DV
COUNTER
DD
4-BIT R
LOCK DETECT
3
D
FRACTION
GND
AV
REG
INTERPOLATOR
1
FRACTIONAL
DD
Low Phase Noise, Fast Settling PLL
1
Figure 1.
D
GND
DIVIDER
MODULUS
÷2
2
REG
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
GENERAL DESCRIPTION
The ADF4193 frequency synthesizer can be used to implement
local oscillators in the upconversion and downconversion
sections of wireless receivers and transmitters. Its architecture
is specifically designed to meet the GSM/EDGE lock time
requirements for base stations. It consists of a low noise, digital
phase frequency detector (PFD), and a precision differential
charge pump. There is also a differential amplifier to convert
the differential charge pump output to a single-ended voltage
for the external voltage-controlled oscillator (VCO).
The Σ-Δ based fractional interpolator, working with the N
divider, allows programmable modulus fractional-N division.
Additionally, the 4-bit reference (R) counter and on-chip
frequency doubler allow selectable reference signal (REFIN)
frequencies at the PFD input. A complete phase-locked loop
(PLL) can be implemented if the synthesizer is used with an
external loop filter and a VCO. The switching architecture
ensures that the PLL settles inside the GSM time slot guard
period, removing the need for a second PLL and associated
isolation switches. This decreases cost, complexity, PCB area,
shielding, and characterization on previous ping-pong GSM
PLL architectures.
V
P
1
D
GND
N COUNTER
+
V
FREQUENCY
3
DETECTOR
INTEGER
P
2
REG
PHASE
SD
GND
V
Frequency Synthesizer
P
3
©2005–2011 Analog Devices, Inc. All rights reserved.
DIFFERENTIAL
SW
AMPLIFIER
REFERENCE
CHARGE
GND
PUMP
R
SET
ADF4193
+
+
SW1
CP
CP
SW2
CMR
AIN–
AIN+
A
SW3
RF
RF
OUT
IN+
IN–
OUT+
OUT–
ADF4193
www.analog.com

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ADF4193BCPZ Summary of contents

Page 1

FEATURES New, fast settling, fractional-N PLL architecture Single PLL replaces ping-pong synthesizers Frequency hop across GSM band in 5 μs with phase settled by 20 μs 0.5° rms phase error at 2 GHz RF output Digitally programmable output phase RF ...

Page 2

ADF4193 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ........................................................................... 2 Specifications..................................................................................... 3 Timing Characteristics ................................................................ 4 Absolute Maximum Ratings............................................................ 5 ESD Caution.................................................................................. 5 Pin Configuration and Function Descriptions............................. ...

Page 3

SPECIFICATIONS SDV = 3 V ± 10 referred to 50 Ω unless otherwise noted. A MIN MAX Table 1. Parameter B Version RF CHARACTERISTICS RF ...

Page 4

ADF4193 Parameter B Version Power-Down 10 DD SW1, SW2, and SW3 R (SW1 and SW2 SW3 75 ON NOISE CHARACTERISTICS ...

Page 5

ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 3. Parameter AV to GND SDV GND Digital I/O Voltage to GND Analog ...

Page 6

ADF4193 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1 CMR Common-Mode Reference Voltage for the Differential Amplifier’s Output Voltage Swing. Internally biased to three-fifths Differential Amplifier Output to Tune ...

Page 7

Pin No. Mnemonic Description 23 R Connecting a resistor between this pin and GND sets the charge pump output current. The nominal voltage bias at SET the R pin is 0.55 V. The relationship between I SET I = 0.25/R ...

Page 8

ADF4193 TYPICAL PERFORMANCE CHARACTERISTICS FREQ. UNIT GHz KEYWORD R PARAM TYPE S IMPEDANCE 50 DATA FORMAT MA FREQ. MAGS11 ANGS11 FREQ. 0.5 0.8897 –16.6691 2.3 0.6 0.87693 –19.9279 2.4 0.7 0.85834 –23.561 2.5 0.8 0.85044 –26.9578 2.6 0.9 0.83494 –30.8201 ...

Page 9

V TUNE 3 CP OUT OUT– DCS1800 Tx SETUP, 60kHz LOOP BW. 1 MEASURED ON EVAL-ADF4193-EB1 EVALUATION BOARD. TIMERS: ICP = 28, SW1/SW2, SW3 = 35. FREQUENCY LOCK IN WIDE BW MODE @ 4 μ s. ...

Page 10

ADF4193 1000 100 7nV 20kHz 10k 100k FREQUENCY (Hz) Figure 16. Voltage Noise Density Measured at the Differential Amplifier Output 100 SW3 90 +85°C SW1/ 80 SW2 +85°C +25°C 70 +25°C –40° –40°C ...

Page 11

THEORY OF OPERATION The ADF4193 is targeted at GSM base station requirements, specifically to eliminate the need for ping-pong solutions. It works based on fast lock, using a wide loop bandwidth during a frequency change and narrowing the loop bandwidth ...

Page 12

ADF4193 The value of MOD is chosen to give the desired channel step with the available reference frequency. Thereafter, program the INT and FRAC words for the desired RF output frequency. See the Worked Example section for more information. PFD ...

Page 13

START WRITE TO R0 ICP SW1/SW2 TIMEOUT TIMEOUT COUNTER COUNTER F ÷4 PFD CHARGE PUMP ENABLE LOGIC EN[64:1] Figure 25. Fast Lock Timeout Counters Differential Amplifier The internal, low noise, differential-to-single-ended amplifier is used to convert the differential charge pump ...

Page 14

ADF4193 REGISTER MAP 8-BIT RF INT VALUE DB23 DB22 DB21 DB20 DB19 DB18 DB17 DBB DBB DBB 4-BIT RF R COUNTER DB23 DB22 DB21 DB20 DB19 DB18 DB17 ...

Page 15

FRAC/INT REGISTER (R0) 8-BIT RF INT VALUE DB23 DB22 DB21 DB20 DB19 DB18 DB17 R0, ...

Page 16

ADF4193 MOD/R REGISTER (R1) 4-BIT RF R COUNTER DB23 DB22 DB21 DB20 DB19 DB18 DB17 REF/2 0 DISABLE 1 ENABLE F2 PRESCALER F1 DOUBLER ENABLE 0 4/5 0 DOUBLER DISABLED 1 8/9 ...

Page 17

PHASE REGISTER (R2) DB15 DB14 DB13 0 P12 P11 P12 12-Bit Phase The phase word sets the seed value of the Σ-Δ modulator. It can be programmed to any integer ...

Page 18

ADF4193 FUNCTION REGISTER (R3) DB15 DB14 DB13 R3, the function register (C3, C2, C1 set respectively), only needs to be programmed during the initialization sequence (see Table 8). CPO GND When the CPO ...

Page 19

CHARGE PUMP REGISTER (R4) RESERVED DB23 DB22 DB21 DB20 DB19 DB18 DB17 Reserved Bits Bit DB23 to Bit DB14 are reserved and should be set to hex code 001 for normal operation. 9-Bit ...

Page 20

ADF4193 POWER-DOWN REGISTER (R5) R5, the power-down register (C3, C2, C1 set respectively) can be used to software power down the PLL and differential amplifier sections. After power is initially applied, there must be writes to ...

Page 21

MUX REGISTER (R6) SIGMA-DELTA AND LOCK DETECT MODES DB15 DB14 DB13 M13 M12 M11 M13 M12 M11 ALL OTHER STATES With C3, C2, and C1 set respectively, ...

Page 22

ADF4193 PROGRAMMING The ADF4193 can synthesize output frequencies with a channel step or resolution that is a fraction of the input reference frequency. For a given input reference frequency and a desired output frequency step, the first choice to make ...

Page 23

The 8:1 loop bandwidth switching ratio of the ADF4193 makes it possible to attenuate all spurs to sufficiently low levels for most applications. The final loop BW can be chosen to ensure that all spurs are far enough out of ...

Page 24

ADF4193 phase swing that occurs when the BW is reduced can be minimized. With dither off, the fractional spur pattern due to the SDM’s quantization noise also depends on the phase word the modulator is seeded with. Tables of optimized ...

Page 25

APPLICATIONS LOCAL OSCILLATOR FOR A GSM BASE STATION Figure 36 shows the ADF4193 being used with a VCO to produce the LO for a GSM1800 base station. For GSM, the REF signal can be any integer multiple of 13 MHz, ...

Page 26

ADF4193 ADI SimPLL Support The ADF4193 loop filter design is supported on ADI SimPLL v2.7 or later. Example files for popular applications are available for download from the applications section of the ADF4193 product page. + 10µF 100nF 100nF 15 ...

Page 27

INTERFACING The ADF4193 has a simple SPI®-compatible serial interface for writing to the device. CLK, DATA, and LE control the data transfer. When LE goes high, the 24 bits that have been clocked into the input register on each rising ...

Page 28

... SEATING PLANE ORDERING GUIDE 1, 2 Model Temperature Range ADF4193BCPZ −40°C to +85°C ADF4193BCPZ-RL −40°C to +85°C ADF4193BCPZ-RL7 −40°C to +85°C ADF4193WCCPZ-RL7 −40°C to +105°C EVAL-ADF4193EBZ1 EVAL-ADF4193EBZ2 RoHS Compliant Part Qualified for Automotive Applications. AUTOMOTIVE PRODUCTS The ADF4193W models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial models ...

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