ADF4193BCPZ Analog Devices Inc, ADF4193BCPZ Datasheet - Page 18

IC PLL FREQ SYNTHESIZER 32LFCSP

ADF4193BCPZ

Manufacturer Part Number
ADF4193BCPZ
Description
IC PLL FREQ SYNTHESIZER 32LFCSP
Manufacturer
Analog Devices Inc
Type
Clock/Frequency Synthesizer (RF)r
Datasheet

Specifications of ADF4193BCPZ

Pll
Yes
Input
CMOS
Output
Clock
Number Of Circuits
1
Ratio - Input:output
2:1
Differential - Input:output
Yes/No
Frequency - Max
3.5GHz
Divider/multiplier
Yes/Yes
Voltage - Supply
2.7 V ~ 3.3 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
32-LFCSP
Frequency-max
3.5GHz
Pll Type
Frequency Synthesis
Frequency
3.5GHz
Supply Current
24mA
Supply Voltage Range
2.7V To 3.3V
Digital Ic Case Style
LFCSP
No. Of Pins
32
Operating Temperature Range
-40°C To +85°C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
EVAL-ADF4193EBZ2 - BOARD EVALUATION EB2 FOR ADF4193EVAL-ADF4193EBZ1 - BOARD EVALUATION EB1 FOR ADF4193
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

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ADF4193
FUNCTION REGISTER (R3)
R3, the function register (C3, C2, C1 set to 0, 1, 1, respectively),
only needs to be programmed during the initialization sequence
(see Table 8).
CPO GND
When the CPO GND bit is low, the charge pump outputs
are internally pulled to ground. This is invoked during the
initialization sequence to discharge the loop filter capacitors.
For normal operation, this bit should be high.
DB15
0
DB14
0
DB13
0
DB12
0
DB11
RESERVED
0
DB10
0
Figure 32. Function Register (R3)
DB9
0
Rev. C | Page 18 of 28
DB8
0
DB7
0
PFD Polarity
This bit should be set to 1 for positive polarity and set to 0 for
negative polarity.
Reserved Bits
The Bit DB15 to Bit DB6 are reserved bits and should be
programmed to hex code 001, and Reserved Bit DB4 should be
set to 1.
DB6
1
DB5
F3
F3
0
1
CPO GND
CPO/CPO GND
NORMAL
DB4
1
DB3
F1
F1
0
1
PFD POLARITY
NEGATIVE
POSITIVE
C3 (0)
DB2
CONTROL
C2 (1)
BITS
DB1
C1 (1)
DB0

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